A novel capacitive sensor for measuring the water-level and monitoring the water quality has been developed in this work by using an enhanced screen printing technology. A commonly used environment-friendly conductive polymer poly(3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) for conductive sensors has a limited conductivity due to its high sheet resistance. A physical treatment performed during the printing process has reduced the sheet resistance of printed PEDOT:PSS on polyethylenterephthalat (PET) substrate from 264.39 Ω/sq to 23.44 Ω/sq. The adhesion bonding force between printed PEDOT:PSS and the substrate PET is increased by using chemical treatment and tested using a newly designed adhesive peeling force test. Using the economical conductive ink PEDOT:PSS with this new physical treatment, our capacitive sensors are cost-efficient and have a sensitivity of up to 1.25 pF/mm.

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There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems.

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Glass is well established as wafer or panel substrate for applications like capping of image sensors or as low loss carrier for integrated passive devices. Glass substrates with higher functionality becomes more attractive for the advanced packaging due the improvement of glass processing and the increased implementation of photonic packaging which is demanded for higher data transfer rates. The through glass vias are therefore essential for the SiP and 3-D integration

Thin film polymers play an essential role in system integration. The mechanical properties of the polymers are crucial for 3-D-Integration and advanced WLP because with the thinning of the silicon wafers, i.e. chips to less than 150 μm, the influence of the polymer layers gets an increasing impact on the mechanical stability of the electronic device. Next generation polymers have entered the market which are tailored to reach the further optimized mechanical property parameter set. This paper will give a guideline for the choice of the optimal polymer based on the demands of the application in relation to the material properties. The main material properties for high reliability are the Young's modulus, tensile strength, elongation at break and coefficient of thermal expansion. Aside of the material properties of the polymer the interaction of the polymer layer with the substrate is important. The material mismatch causes for example warpage and material cracking; the main impact factor being the residual stress in the layers in relation to the fracture toughness of the material and the interface. The warpage is an issue for the processing and the assembly process. The focus of our investigation is on properties of polymers on silicon substrates. The development of stresses in the polymer layers is measured and analyzed for different polymers (BCB, PI, PBO). The residual stress in a thin polymer film is measured by the warpage of the substrate in relation to different temperatures depending on the application. The estimation of stress-temperature behavior allows to develop processing concepts for a stress reduction being essential for 3-D integration. The generated stress drives cracking which leads to the effect that the impact of the forces should be taken into account for the quantification of the fracture toughness. The relation between the stress as the driving force and the fracture toughness are further discussed in details. A comprehensive study of- the mechanical polymer properties is essential for high reliable devices