In this paper a training model of a processor and its CPLD implementation are presented. The processor has a simplified instruction set and architecture in order to fit into a 256 macrocell CPLD. The described model helps students in computing to familiarize practically with functioning of a processor through simulation and implementation in a programmable logic device, as well as development of their own instructions and experiments with signal flow within a processor. The processor has been simulated and synthesized for the Xilinx XC2C256 CoolRunner-II CPLD and tested in the environment of the Starter Kit XC2-XL.
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