Dynamic and non-linear systems have been used to generate random bits in high-security applications for decades. In this perspective, due to their stochastic characteristic, chaotic systems have been emerging as the natural choice for the generation of random bits. This paper presents the design and the implementation of a chaos-based true random number generator and a chaos-key based data encryption scheme for secure communications. The mathematical expression of the dynamic system is presented and analyzed to evaluate the possibility of chaos occurrence. Then, the chaotic system is realized at the circuit level using 130 nm CMOS technology to generate random bit sequences, which are utilized in data encryption. Chaotic signal outputs of the chaos-based random number generator circuit are sampled at a maximum frequency of 50 MHz, enabling a high throughput of random bits. The core of the chaotic circuit consumes 630µW in static mode and a maximum of 660µW in running mode. The chaos-based one-time pad encryption scheme using the chaos-key generator shows the advantages of using this random number generator in secure communications. In this context, the data secrecy is compared to the advanced encryption standard AES128. Moreover, the design is simulated in different working conditions such as voltage supply and temperature variations, where it is shown that the random bit output benefits from a high entropy per bit and passes the standard statistical test suite (NIST) for cryptographic applications. INDEX TERMS Chaos, random key, security, CMOS, true random number generator, one-time pad encryption, image encryption, and NIST.
Low-power devices used in Internet-of-things networks have been short of security due to the high power consumption of random number generators. This paper presents a low-power hyperchaos-based true random number generator, which is highly recommended for secure communications. The proposed system, which is based on a four-dimensional chaotic system with hidden attractors and oscillators, exhibits rich dynamics. Numerical analysis is provided to verify the dynamic characteristics of the proposed system. A fully customized circuit is deployed using 130 nm CMOS technology to enable integration into low-power devices. Four output signals are used to seed a SHIFT-XOR-based chaotic data post-processing to generate random bit output. The chip prototype was simulated and tested at 100 MHz sampling frequency. The hyperchaotic circuit consumes a maximum of 980 $$\upmu $$ μ W in generating chaotic signals while dissipates a static current of 623 $$\upmu $$ μ A. Moreover, the proposed system provides ready-to-use binary random bit sequences which have passed the well-known statistical randomness test suite NIST SP800-22. The proposed novel system design and its circuit implementation provide a best energy efficiency of 4.37 pJ/b at a maximum sampling frequency of 100 MHz.
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