Triangular-current-mode (TCM) modulation guarantees zero-voltage-switching across the mains cycle in AC-DC power converters, eliminating hard-switching with a minor ≈ 30 % penalty in conduction losses over the conventional continuous current mode (CCM) modulation scheme. TCM-operated converters, however, include a wide variation in both switching frequency and switched current across the mains cycle, complicating an analytical description of the key operating parameters to date. In this work, we derive an analytical description for the semiconductor bridge-leg losses in a TCM AC-DC converter, including the rms current and/or conduction losses, switching frequency, and switching losses. For SiC MOSFETs, we introduce a new loss model for switching losses under zero-voltage-switching, which we call "residual ZVS losses". These losses include the constant Coss losses found in previous literature but must also add, we find, turn-off losses that occur at high switched currents. The existence and modeling of these turn-off losses, which are due to currents flowing through the Miller capacitance and raise the inner gate source voltage to the threshold level and accordingly limit the voltage slew rate, are validated on the IMZA65R027M1H 650 V SiC MOSFET. The complete loss model-and the promise of TCM for high power density and high efficiency-is validated on a 2.2 kW hardware bridge-leg demonstrator, which achieves a peak 99.6 % semiconductor efficiency at full load. The proposed, fully-analytical model predicts bridge-leg losses with only 12 % deviation at the nominal load, accurately including residual ZVS losses across load, modulation index, and external gate resistance.

This paper presents a comprehensive analysis of non-linear voltage-dependent capacitances of vertical SiC power MOSFETs with lateral channel, focusing specifically on fast switching transients. The capacitance-voltage (C-V) device characteristics, (Cgs, C gd , C ds), being dependent on both Vgs and V ds , are extracted by means of two-dimensional Technology Computer Aided Design (TCAD) simulations for a commercially available device in both off-and on-state modes. Different compact models for the power MOSFET are investigated, each employing a three inter-terminal capacitance model as typically used in power electronics. The performed analysis provides a detailed explanation for the importance of taking into account the dependence of C gd , Cgs and C ds on both of the voltages Vgs and V ds. This is especially important for fast switching transients (in the range of 10 ns) in order to accurately predict switching losses, driver losses, current and voltage slopes, as well as current and voltage delays. As direct measurements for C gd , Cgs and C ds in dependence of both Vgs and V ds are highly demanding, the results presented in this paper increase the understanding of both the underlying effects as well as of the trade-offs between accuracy and computational complexity made by simplifying device models. In turn, this information is highly beneficial for enabling accurate and computationally efficient automated design procedures for power electronics.

For three-phase AC-DC power conversion, the widely-used continuous current mode (CCM) modulation scheme results in relatively high semiconductor losses from hardswitching each device during half of the mains cycle. Triangular current mode (TCM) modulation, where the inductor current reverses polarity before turn-off, achieves zero-voltage-switching (ZVS) but at the expense of a wide switching frequency variation (15× for the three-phase design considered here), complicating filter design and compliance with EMI regulations. In this paper, we propose a new modulation scheme, sinusoidal triangular current mode (S-TCM), that achieves soft-switching, keeps the maximum switching frequency below the 150 kHz EMI regulatory band, and limits the switching frequency variation to only 3×. Under S-TCM, three specific modulation schemes are analyzed, and a loss-optimized weighting of the current bands across load is identified. The 2.2 kW S-TCM phase-leg hardware demonstrator achieves 99.7 % semiconductor efficiency, with the semiconductor losses accurately analytically estimated within 10 % (0.3 W). Relative to a CCM design, the required filter inductance is 6× lower, the inductor volume is 37 % smaller, and the semiconductor losses are 55 % smaller for a simultaneous improvement in power density and efficiency.

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