The HEXITECMHz ASIC is the next generation of the STFC's High Energy X-ray Imaging Technology (HEXITEC). With a ×100 increase in the camera frame rate to 1 MHz, the new ASIC is capable of delivering fully spectroscopic X-ray imaging at photon fluxes of 2×106 photons s-1 mm-2. The improved flux capability ensures the relevance of the technology at a new generation of difraction-limited storage ring (DLSR) synchrotrons as well as enabeling dynamic spectroscopic imaging with sub-keV energy resolution to be carried out on millisecond timescales. In this paper preliminary results from X-ray testing of a 0.3 mm thick p-type Si sensor and 2.0 mm thick HF-CdZnTe sensor at the Diamond Light Source Synchrotron are presented for the first time. Each module consists of 80 × 80 pixels on a 250 μm pixel pitch operated at a temperature of 20°C and a frame rate of 1 MHz. For these preliminary measurements, testing was completed using a prototype test system which limited readout to a portion of the 1 MHz output sampled over an SPI test interface at ∼50 Hz. Despite this limitation these measurements allow the spectroscopic performance of the ASIC to be characterised ahead of the full DAQ system. The prototype detectors were characterised using monochromatic X-rays with energies 12–35 keV at fluxes of (0.6 – 2.5) × 106 photons s-1 mm-2. At an X-ray energy of 12 keV, the energy resolution of the p-type Si and HF-CdZnTe detectors were measured to be 1.0 keV and 1.1 keV respectively. At the higher energies of 20 keV and 35 keV the energy resolution in the HF-CdZnTe was measured to be 1.2 keV and 1.4 keV respectively.
Flip-chip bonding is a common method for joining application-specific integrated circuits (ASIC) to pixel sensors in order to build hybrid radiation detectors for X-rays and gamma-rays. STFC-RAL is using two methods for the interconnects between ASIC and sensor pixels. These are either indium bumps which are deposited on ASIC and sensor prior to bonding or alternatively electrically conductive adhesive dots are printed on the sensor pixel array and flip-chip bonded to gold studs attached to each pixel of the ASIC. Conventionally the indium deposition is carried out on wafer-scale using a photolithographic lift-off process. Sensor and ASIC with indium bumps are singulated from wafers afterwards. Some sensor material (e.g. CdZnTe) which is required for high-energy and high-flux X-ray detectors at X-ray Free Electron Lasers (XFEL) or in other scientific experiments is only available as individual die instead of wafers. The stencil printing of conductive epoxy dots onto those sensor dies together with gold ball studding of ASICs is a suitable method for those dies. However, due to the size of printed epoxy dots this method has a limited pixel pitch and is currently only used for sensors with 250 μm-pitch or for larger pitch. A novel method for indium deposition was developed for such dies. A shadow mask with small apertures is optically aligned to the pixel array and mechanically clamped to the sensor die. After indium evaporation onto this assembly and after removal of the mask, indium bumps as small as 50 μm with a height of ∼ 5 μm are deposit onto the pixel array of the sensor. The same is done for a matching ASIC. A comparison of these two methods indicates that indium bumps created by the shadow mask technique are approx. half the size of the epoxy dots and comparable with gold studs. Using this method, at present a pitch of 100 μm for those indium bumps can be achieved and development for further improvement towards smaller pitch is carried out currently. This novel indium deposition method is compared with the conventional wafer-scale indium lift-off method and the epoxy/gold stud flip-chip bonding in terms of interconnect quality, bond yield, and suitability for hybrid radiation detectors.
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