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Abstract:In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1 ps. The power consumption of the proposed ADPLL at 500 MHz frequency is 820 µW. The proposed ADPLL is simulated in 180 nm CMOS with Hspice and verified by MATLAB.

Abstract:In this paper, an ultra low power 15-bit digitally controlled oscillator (DCO) is proposed. The proposed DCO is designed based on a segmental coarse-tuning stage which employs novel Schmitttrigger based hysteresis delay cells (HDC) as well as digitally controlled varactor (DCV) in the fine-tuning stage. Simulation of the proposed DCO using TSMC 180 nm model achieves controllable frequency range of 191 MHz ∼ 850 MHz with a wide linearity. Monte Carlo simulation demonstrates that the time-period jitter due to random power supply fluctuation is under 124.8 ps and the power consumption is 137 µW at 215 MHz with 1.8 V power supply.

High sampling frequency requirement in delta–sigma modulator (DSM) is one of the limiting factors toward its employment in high-frequency application, such as software-defined radio (SDR) transmitters. In this paper, a complexity-reduced parallel time-interleaved DSM is proposed to reduce the clock speed requirement of DSM transmitters. The complexity of the proposed parallel time-interleaved DSM is reduced by input delay blocks and input downsampler blocks in comparison to conventional time-interleaved DSMs. Simulation results show that the clock speed requirement of DSM transmitter is reduced four times by using the proposed four-branch complexity-reduced time-interleaved DSM, while signal quality is maintained.