An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

Abstract

Abstract:In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding the reference frequency. An efficient glitch removal filter and a new low power DCO are also introduced in this letter. The DCO achieves a reasonably high resolution of 1 ps. The power consumption of the proposed ADPLL at 500 MHz frequency is 820 µW. The proposed ADPLL is simulated in 180 nm CMOS with Hspice and verified by MATLAB.

Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator

“…This implementation will consume high power due to its technology in design. The binary frequency searching method is also applied in Abadian et al (2011). In that method, time domain frequency estimation algorithm is introduced to get the fast lock mechanism, but it is much more complicated that the proposed design.…”

“…The PLL have problems such as noise coupling with power supply, substrate induced noise, sensitivity to process the parameters. All PLL is composed of all digital components, so it has high resistance to supply noise, temperature variation and process parameters (Zhao et al, 2010;Abadian et al, 2011). Some conventional designs are introduced in (Shuai et al, 2013;Wu et al, 2010), a complicated way, such as binary searching or time to digital converter (TDC) is used for locking which results in power and area consumption.…”

A compact and low-power wireless receiver for implanted medical backscatter

“…The digital loop is similar to the proportional-integral loop filter in [16] and drives the VCO via two ports-the fine bits to turn on/off the switchable capacitors at VCO nodes and the other coarse bits to a voltage sigma-delta DAC that effectively regulates the VCO supply and hence adjusting the VCO frequency [17]. The circuit is also much simpler than the ADPLL is [23], [26] and [27]. The phase interpolation block can also be gated to work only when reference comparison edge is coming, thus saving a large amount of power.…”

A low-power dual band all digital PLL with precision dual mode DCO and digital linearization control circuits

“…Moreover, PLL reference [13] is similar to the reference [12], the only difference being designed of the controlled oscillator with digital signal. The oscillator in [13] is based on changing the MOS driving strength dynamically using a fixed capacitance loading with high resolution, but the power consumption by this structure is high. Our recently developed dual band DCO [19] operates in two different frequency ranges.…”