Design of an ultra-low power, low complexity and low jitter PLL with digitally controlled oscillator

Abstract

This paper proposes a new area-efficient, low-power and low-jitter phased-locked loop (PLL) architecture working off a low frequency reference. In this paper, new PLL is proposed with a new locking procedure with low complexity which results in ultra low power design. The main challenge to design the proposed PLL is to keep the area small while meeting the required low jitter. The proposed method was designed using only two up-down counters for finding the reference frequency. An efficient glitch removal filter and new low power DCO also introduced in this paper. The proposed DCO achieves a reasonably high resolution of 1ps. The PLL architecture was demonstrated for different frequency ranges from 100-400 MHz. The power consumption of proposed PLL at 500 MHz frequency is 820 µW. The proposed PLL is simulated in 180 nm with Tanner EDA and verified.