Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator

Low‐clock‐speed time‐interleaved architecture for a polar delta–sigma modulator transmitter

“…For instance, the clock speed requirement of the proposed time-interleaved polar DSM transmitter baseband part reduces four times (from 245.76 MHz to 61.44 MHz) using the four-branch time-interleaved structure while maintaining the signal quality ($41 dB). Furthermore, the comparison results of the proposed time-interleaved polar DSM transmitter baseband part and time-interleaved polar DSM transmitter baseband parts based on the methods described in Embrahimi and others and Khoini-poorfard and others [10,25] (Figure 3) and Kozak and others and Erfani Majd and others [26,27] (Figure 4) are listed in Table 2. They have exhibited almost the same SNDR performance for different numbers of parallel branches.…”

“…The hardware growth of this time-interleaved polar DSM transmitter baseband part becomes proportional to M 2 by increasing the number of parallel branches (M). In Kozak and others and Erfani Majd and others [26,27], this high hardware complexity problem is reduced by deriving the polyphase equivalent transfer functions of DSM integrators based on feedforward and feedback matrices.…”

“…The proposed time-interleaved polar DSM transmitter baseband part mainly uses the upsampling technique by applying the same input signal (with M times lower sampling rate) to all the M parallel branches. Therefore, in this case (unlike the time-interleaved polar DSM transmitter baseband part based on techniques presented in Kozak and others and Erfani Majd and others [26,27]), there is no need for delay and downsampler blocks at the input. Each input delay block in the architecture based on Kozak and others and Erfani Majd and others [26,27] includes one register.…”

“…Therefore, in this case (unlike the time-interleaved polar DSM transmitter baseband part based on techniques presented in Kozak and others and Erfani Majd and others [26,27]), there is no need for delay and downsampler blocks at the input. Each input delay block in the architecture based on Kozak and others and Erfani Majd and others [26,27] includes one register. If we consider the N-bit input signal, each input delay block is included in the N 1-bit register.…”

Spectrally efficient multicarrier modulation system for visible light communication

“…TCM uses set partitionaing and small number of states at the transmitter and Viterbi decoding algorithm is applied to the trellis, with surviving partial paths corresponding to partial signal sequences that are closest to the received sequences. DSM is a modulation technique for encoding analog signal into digital signal [9]- [12]. It is used to convert high bit-count, low-frequency digital signals into lower bit-count, higher-frequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC).…”