Films of tantalum pentoxide (Ta2O5) have been fabricated by use of different precursor materials, deposition techniques and annealing procedures. Several analytical methods were appliedto study the layers. Fundamental properties and new data are reportedand related to practical features that are of importance in device design and manufacturing of advanced, highly integrated devices. This overview may facilitate the choice of an optimal combination of precursor, deposition technique and corresponding annealing procedure for aspecific application of these films in microelectronics, since the electrical properties reveal the potential of Ta2O5 films for the use in 64Mbit and 256Mbit DRAM devices as high dielectric constant material.
Ta2O5 and Nb2O5 films were deposited using the Lam Research Integrity™ reactor. The chemical precursors used were pentaethoxides of Ta and Nb. Typical films were deposited at a rate of 4 nm/min with uniformities of <1.5% lσ in the presence of O2 at 470°C. Annealing the Ta2O5 films did not change the O/Ta ratio. Annealing the Nb2O5 films increased the O/Nb ratio to 2.5/1 at 850°C. Interfacial SiO2 grew to 4 nm after annealing at 850°C for both Ta2O5 and Nb2O5. The as-deposited films were amorphous, but became crystalline above 600°C and 700°C for the Nb2O5 and Ta2O5 films respectively. The TEM observations on crystallization is supported by x-ray diffraction data.
Tantalum pentoxide (Ta2O5) films were deposited from the reaction of tantalum pentaethoxide (Ta(OC2H5)5) and oxygen (O2) using the Lam Research Corporation DSM™9800 advanced LPCVD reactor. Typical films were deposited at a rate of 0.9 – 1.1 nm/min at 400°C. The films were stoichiometric with an O/Ta ratio of 2.57/1.00 and excellent compositional uniformity. Conformity was >95% indicating that the process is surface reaction rate limited. Films with non‐uniformities <2.2% were deposited on 300 mm wafers. The deposited non‐uniformity on 150mm and 200mm wafers was <2.0% ‐1σ within a wafer, wafer to wafer within a batch, and batch to batch. The dielectric constant for as‐deposited films was 22–24, and as high as 34 for films which were heat treated. Various post deposition heat treatments were performed to improve the capacitor's electrical properties. Superior results were obtained from rapid thermal annealing (RTA) in N2O compared with RTA in O2 and two‐step UV‐O3 followed by high temperature annealing in dry O2. Values for the leakage current of <10-8 A/cm2 at 1.2 volts negative bias (worst case) and breakdown >5 MV/cm at 1.6μΑ with tegox<2.5 nm have been obtained. These values meet the requirements for 256 Mbit DRAM memory devices Bottom and top electrode formation and integration issues are also addressed.
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