A capacitance-to-pulse duration converter, specifically\ud designed for interfacing capacitive sensors, is presented. The\ud operating principle is a double slope approach implemented using\ud transconductor-based Miller integrators. The main strengths of\ud the proposed circuit are: 1) intrinsically small sensitivity to temperature;\ud 2) simplicity of trimming offset and gain to correct the\ud sensor parameter spread; and 3) fast wake-up time. The circuit\ud nonidealities are analyzed in order to identify the elements responsible\ud for the residual temperature sensitivity and jitter on the\ud pulse duration. The effectiveness of the method is demonstrated by\ud measurements performed on a prototype, designed and fabricated\ud using the 0.35 m, 3.3 V Bipolar-CMOS-DMOS process BCD6 of STMicroelectronics

A compact, low power interface for capacitive sensors, is described. The output signal is a pulse width modulated (PWM) signal, where the pulse duration is linearly proportional to the sensor differential capacitance. The original conversion approach consists in stimulating the sensor capacitor with a triangular-like voltage waveform in order to obtain a square-like current waveform, which is subsequently demodulated and integrated over a clock period. The charge obtained in this way is then converted into the output pulse duration by an approach that includes an intrinsic tunable low pass function. The main non idealities are thoroughly investigated in order to provide useful design indications and evaluate the actual potentialities of the proposed circuit. The theoretical predictions are compared with experimental results obtained with a prototype, designed and fabricated using 0.32 mu M CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025 x 515 mm(2) and is marked by a power consuption of 84 mu W. The input capacitance range is 0-256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ppm/degrees C

A compact converter from capacitance to pulse width, suitable for interfacing integrated capacitive sensors is described. The circuit has been designed and fabricated using 0.32 μm/ 3.3 V CMOS devices from the BCD6s process of STMicroelectroncs and occupies an area of 1025 × 515 μm2. Measurements performed on the test chip showed an excellent linearity, a temperature drift of 300 ppm/”C, and power consumption as low as 84 μW for continuous operation

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An interface circuit for integrated capacitive sensors with pulse width modulated output is presented. The circuit is based on an original architecture implementing offset and low frequency noise cancellation by means of chopper modulation. Electrical simulations, performed on a prototype designed using 0.32 mu m/3.3V CMOS devices, showed that a sensitivity to temperature lower than 10 ppm/degrees C with a power consumption of 66 mu W can be obtained with this approach

Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow values. A prototype circuit, which was designed with the 0.35- m bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations

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A procedure to obtain class-AB Operational Transconductance Amplifiers (OTA) from conventional class-A cells is presented. Application to a wide swing CMOS OTA is described. The results of simulations, based on a commercial process, are reported to demonstrate the effectiveness of the method and to illustrate its advantages and limitations