Design automation techniques are playing an important role in controlling the complexity of system design. Our work is inscribed in tlw &sign automation of microprocessor-based systems which necessitates the design of interjizces for system integration. During the interface synthesis if is required to validate the timing of a design yet to be iinplemented. In this paper we present a novel methodology to timing analysis that can determine tight bounds on interjlzce path delays based on the given timing information. The timing analysis for synthesis problem is formulated as a combinatorial optimization problem using interval arithmetic techniques. L IntroductionThe design of interface circuits emphasizes the synthesis of cnntrol logic [4]. Other resea.mh work [9] indicates that controller design can benefit from a delay-insensitive design methodology which produces robust circuits that behave correctly even in the presence of variations on gate and wire delays. However it is not always possible to neglect timing information corresponding to either internal circuit delays or constraints on the environment for proper circuit operation [10]. This is particularly true in the design of microprocessor-based systems whose protocols specify {ieadlines to meet.In this paper we discuss a Petri net based repment.ation forma.hsm that allows us to nmsou about known circuit path delays and environmental timing constraints. Although our approach shares similarities with other work in the area of interface synthesis and controller design, our aim is to break a recurrent problem encountered during :synthesis: a solution must be first offered to be able to (determine if it satisfies the design constraints. The main :result of this paper is a novel approach to time analysis that "bwdcs this cycle by finding bounds on the delays of the circuit to be synthesized before the actual circuit implementation takes place.In the following section we survey related work. Our representation formaiism is based on a timed Petri net which is presented in section 3. Section 4 is devoted to the discussion of the details of the timing anrdysis methodolo-gy. An example is given in section 5 to illustrate our approach. Finally future work is pointed in the conclusions. Related workA microprocessor-based system is a collection of components which operate independently of one another but are required to communicate and synchronize with the rest of the system through communication structures called buses. The interface design problem arises during system integration when components are blended into a single entity. In general the design of an interface involves not only electrical and logical signal conditioning but also protocol con-
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.