Timing analysis for synthesis in microprocessor interface design

Abstract

Design automation techniques are playing an important role in controlling the complexity of system design. Our work is inscribed in tlw &sign automation of microprocessor-based systems which necessitates the design of interjizces for system integration. During the interface synthesis if is required to validate the timing of a design yet to be iinplemented. In this paper we present a novel methodology to timing analysis that can determine tight bounds on interjlzce path delays based on the given timing information. The timing analysis for synthesis problem is formulated as a combinatorial optimization problem using interval arithmetic techniques. L IntroductionThe design of interface circuits emphasizes the synthesis of cnntrol logic [4]. Other resea.mh work [9] indicates that controller design can benefit from a delay-insensitive design methodology which produces robust circuits that behave correctly even in the presence of variations on gate and wire delays. However it is not always possible to neglect timing information corresponding to either internal circuit delays or constraints on the environment for proper circuit operation [10]. This is particularly true in the design of microprocessor-based systems whose protocols specify {ieadlines to meet.In this paper we discuss a Petri net based repment.ation forma.hsm that allows us to nmsou about known circuit path delays and environmental timing constraints. Although our approach shares similarities with other work in the area of interface synthesis and controller design, our aim is to break a recurrent problem encountered during :synthesis: a solution must be first offered to be able to (determine if it satisfies the design constraints. The main :result of this paper is a novel approach to time analysis that "bwdcs this cycle by finding bounds on the delays of the circuit to be synthesized before the actual circuit implementation takes place.In the following section we survey related work. Our representation formaiism is based on a timed Petri net which is presented in section 3. Section 4 is devoted to the discussion of the details of the timing anrdysis methodolo-gy. An example is given in section 5 to illustrate our approach. Finally future work is pointed in the conclusions. Related workA microprocessor-based system is a collection of components which operate independently of one another but are required to communicate and synchronize with the rest of the system through communication structures called buses. The interface design problem arises during system integration when components are blended into a single entity. In general the design of an interface involves not only electrical and logical signal conditioning but also protocol con-

Assessing the feasibility of interface designs before their implementation

“…Our model is suitable for symbolic timing analysis that finds the tightest bounds on the unknown interface path delays before the actual circuit is implemented [4]. Delay-insensitivity [1] is a special case of circuit design in which timing constraints are satisfied by any implementation regardless of the circuit delays.…”

“…In this paper we address the problem of verifying that such an interface design is feasible before synthesis is attempted, i.e. that the interface generates the necessary events at the expected times to accomplish the intended inter-component communication.Thus it is possible to avoid the design-synthesis-verification cycle: a design is first synthesized, then checked against its specification, and if verification fails the process is repeated.In order to be able to describe the protocols used by offthe-shelf microprocessor components we have developed a representation of timed behaviors based on a Petri net model which allows us to reason about circuit delays and environmental timing constraints.Our model is suitable for symbolic timing analysis that finds the tightest bounds on the unknown interface path delays before the actual circuit is implemented [4]. Delay-insensitivity [1] is a special case of circuit design in which timing constraints are satisfied by any implementation regardless of the circuit delays.…”

A probabilistic timing analysis for synthesis in microprocessor interface design

“…The work cited above requires that all the circuit delays be known prior to timing verification. The main contribution of [3] is a procedure capable of determining bounds on the path delays ahead of the implementation phase. It is now possible to detect specification inconsistencies and to guide the implementation phase.…”

“…In this section we extend the timed Petri net framework presented in [3] to treat operational delays as random variables. We use this extension to obtain reliability estimates during both synthesis and verification.…”

“…An important goal that our work achieves is to break a recurrent problem encountered during synthesis: a solution must first be found to be able to determine if it satisfies the design constraints. We use a timing analysis for synthesis (TAFS) approach [3], also known as symbolic verification, which treats the interface path delays symbolically and finds the tightest bounds on those delays that satisfy the given timing constraints. Timing information is usually described as a pair of minimum/maximum values which defines an interval.…”