In this paper, a novel flip chip interconnect structure called Bond-On-Lead (BOL) and its ability to reduce stress in the sensitive sub-surface ELK (Extra Low K) layers of the die is presented. BOL is a new low cost flip chip packaging solution which was developed by STATSChipPAC to dramatically reduce the cost of flip chip packaging. The BOL solution allows for efficient substrate routing by virtue of the use of narrow BOL pads and the removal of solder mask in the area of the BOL pads, which eliminates the limitations associated with solder mask opening sizes and positional tolerances. In addition to the compelling cost benefits, modeling results are confirmed with empirical reliability testing data to show that BOL is superior to the traditional Bond-on-Capture Pad (BOC) configuration from a mechanical stress and reliability perspective. The focus of this paper is on the theoretical analysis of the stress, strain, and warpage associated with the BOL configuration compared with the traditional BOC structure. For the package deformation, the global finite element method is used to simulate the package warpage. For the local bumping reliability, the focus is on the ELK layers which are the critical locations affecting the package's reliability. The local finite element simulation is conducted to compare the critical ELK layers stresses with BOL structure vs. with traditional BOC structure.
The molded underfill (MUF) has become one of the trends in the IC packaging industry due to its simplification of assembly process steps and the saving of the cost. However, for the fine pitch flip chip bumping array, the void generation is one serious issue causing the short of the electrical connections and the cracking of the bumps. In this paper, the main focus is to predict the void generation and to compare with the experimental data. The early stage FEM numerical simulation not only can predict the risk of voids but also provide the best economic approach without the need to spend trial and error budget. A multiple segments substrate strip, with totally 64 packages populated on it, is used in the experiment. The manufacturing process parameters are programmed and recorded for comparison. The filling, packing, and curing of molding compound are carefully chosen in order to compare their effects. After the assembly process, each package is scanned with C-SAM inspection to check if the voids appear. For FEM numerical simulation, only one segment of the substrate strip, with totally 16 packages, is modeled to save computational resources and time. However, all the bumps, on each of the package, are modeled in order to check how the flow field is affected by the packages. In conclusion, we have obtained good match of experimental vs. simulation data. The prediction of voiding location is very close to each other.
In this paper, the thermal performance data of theta jc (Rth-JC) and theta ja (Rth-JA) of a flip chip ball grid array device with heat spreader, fcBGA-H, is measured. For Rth-JC, various boundary conditions for the thermal resistance modeling are considered and discussed. A transient measurement method is used to obtain the temperature responses of the diodes, as a function of time. The structure functions of the diodes are measured, and based on the structure functions, the thermal resistances are calculated. With the structure functions, the impact of package configurations are better viewed and demonstrated, and a novice measurement technique is also proposed here to measure the thermal resistance of junction to die, Rth-JD. With this experimental setup, there is no need to use the thermal couples. The traditional drilling hole for thermal couple and thermal couple itself will change the package configuration and heat dissipation path, and, therefore, impact the accuracy of the measurements.
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