Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure

Ouyang, Eric; Chae, MyoungSu; Chow, Seng Guan; Emigh, Roger; Joshi, Manjusha; Martin, R.; Pendse, R.

doi:10.4071/isom-2010-tp2-paper1

Cited by 16 publications

(4 citation statements)

References 5 publications

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“…Prior characterizations on 65nm Low-K and lower Si nodes with ELK (Extra Low K-Dielectric) have shown the BoL structure as being more robust with respect to ILD crack protection vs. the comparable SMD joint configuration shown above. These findings have been proven by empirical data as well as the Finite Element Modeling (FEM) and have been reported extensively in prior papers [4], [5].…”

Section: Assembly Process Characterizationsupporting

confidence: 62%

Low cost Cu column fcPoP technology

Eslampour¹,

Kim²,

Park³

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Package-On-Package (PoP) is now a wide-spread 3D package technology used in Smartphones, TABLET devices, and in some Gaming applications. The vertical integration of high speed memory packages such as DDR-II and form factor reduction are the main drivers for adoption of these package types. Continuous trends in bump pitch reduction and performance improvement in combination with higher density Si have created the need for Cu column design for Flip Chip bumps. Also, adoption of Cu column and the associated Bond-on-Lead (BoL) technology provide substrate cost reduction through design rule relaxation, which is key for cost sensitive PoP packages and consumer electronics, in general.

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Section: Assembly Process Characterizationsupporting

confidence: 62%

Low cost Cu column fcPoP technology

Eslampour¹,

Kim²,

Park³

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…Prior work involving Thermo-Mechanical stress simulation on Cu-column on BOL structure has shown significant stress reduction on bump as well as on silicon dieelectric material (ELK) [4]. The same elements make CuBOL technology a superior one for Empirical data was generated using CuBOL technology on 28N/ELK TV; with 10x10mm sq.…”

Section: Application Of Cubol On Advanced Silicon Nodementioning

confidence: 99%

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

Movva

Bezuk

Bchir

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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An innovative packaging solution -'Cu-column on BOL' (CuBOL) is developed that dramatically reduces flip chip package cost and offers superior product reliability, thus posing an important flip chip package solution in mobile product applications. The CuBOL technology, utilizing the fcCuBE TM offering by STATS ChipPAC, entails proprietary changes in the bump interconnect structure using Cu-column bump attached to a narrow trace or bond-on-lead (BOL) on substrate without any solder resist confinement (open SR) in the peripheral I/O region of the die. This enables improved routing efficiency on the substrate top layer thus allowing conversion of a flip chip substrate from original 4L to 2L without compromising functionality. The cost of the flip chip package is lowered by means of reduced substrate layer count, removal of solder on pad (SOP) and solder mask and relaxed design rules. When combined with high density substrate strip design and molded underfill (MUF), this process further lowers the manufacturing cost. Use of Cucolumn bump with Pb-free solder cap used in CuBOL technology helps achieve a 'Green' package solution, which is complimented by improved package reliability benefits achieved by a remarkable reduction of package stress due to the resulting interconnect structure. The CuBOL technology has also been proven to protect the extreme or ultra low K (ELK/ULK) die-electric against cracking or delamination as confirmed with empirical data generated using advanced silicon node test vehicles and further substantiated by thermomechanical simulation results. This paper summarizes the multidisciplinary effort undertaken to develop and qualify CuBOL technology using a 7x7 mm fcTFBGA package as test vehicle (TV). Existing substrate design in a 1-2-1 laminate build-up substrate was comfortably routed into 2 layer substrate design, yet maintaining the I/O count, original bump lay-out & ball map and the original bump-to-ball netlist by applying more efficient routing scheme offered by CuBOL technology. TV wafers were bumped using the composite structure of Cucolumn with a Pb-free solder cap. Different aspect ratio of Cu-column height to solder cap height were evaluated to find the optimal one to ensure robust joint formation. Flip chip attach process using composite Cu-column bump with narrow BOL pad was studied in detail in terms of impact of design, and process factors on non-wet, solder short and warpage performance. Side by side comparison of original 4L design and CuBOL 2L was conducted in terms of strip and unit warpage finding significant benefits with the latter. Ultimately, extensive reliability testing was conducted on the packaged units assembled using CuBOL technology by subjecting through a battery of JEDEC standard stress tests for example -preconditioning, temperature cycling (TC), high temperature storage(HTS) and un-biased HAST and excellent reliability results with adequate margins were obtained.Subsequent interception of CuBOL technology into advanced silicon node TVs showed improved package reli...

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“…The robust margin seen with respect to ILD crack is partly due to the performance of fcCuBE achieved based on Cu column and BOL design, which has proven to increase the ILD crack process margin through both experimental data and modeling validation [8].…”

Section: Cu Column and Bol Design In Fccubementioning

confidence: 99%

Advancements in Package-on-Package (PoP) technology, delivering performance, form factor & cost benefits in next generation Smartphone processors

Eslampour¹,

Joshi²,

Park³

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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The explosive growth and adoption of Smartphones in the mobile market has led to its proliferation into feature-rich phones. Prismark's estimate of total handset shipped globally in 2012 stands at 1.8 Billion (B) units, with Smartphones taking 700 Million (M) unit share, and the projected total market size by 2013 is at 2.3B units. More importantly, the projected Compounded Average Annual Growth Rate (CAAGR) for Smartphone tier is at 21% whiles the projected CAAGR for the historic feature-rich and low-end phone through the same timeframe is -8% and -6%, respectively. As a result of this growth rate increase in Smartphones, adoption of Package-on-Package (PoP) technology, which has long been reserved for high-end phones, and which also benefits from the vertical integration of DRAM memory package and Logic or Application Processor (AP) package, has been increasing mainly due to its capability of addressing the board space limitation faced with, in most Smartphone devices. Additionally, this vertical integration, which results in shorter signal path between the Memory and AP device, leads to better Signal Integrity (SI) and faster data-rate transfer, hence improving the overall device performance. With the more widespread adoption of Smartphones, two other trends have simultaneously been taking place that include downward cost pressure and thinner profile handsets. This latter trend in thickness reduction has long been putting pressure on PoP height reduction, which in turn has resulted in development of various PoP technologies to address the thinner profile package requirements [1]. One particular PoP package type known as Molded Laser-Via Package (MLP) has become popular over the traditional Bare Die PoP type in addressing this height reduction due to its advantages for height reduction and improved warpage performance [2]. However, to address the cost sensitive handset segment and to provide a low cost PoP solution for lower tier Smartphones, recently Bare Die PoP in a very thin profile measuring only to 1.2mm max stack height and with 0.4mm Memory Interface (MI) pitch has been developed and qualified. This paper describes the features of this package, proliferation of Bare Die PoP into larger body packages and challenges that body size-increase brings about, performance comparison of Bare Die PoP to its more advanced MLP counterpart, and some advancements seen in MLP package technology.

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Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure

Cited by 16 publications

References 5 publications

Low cost Cu column fcPoP technology

Low cost Cu column fcPoP technology

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

Advancements in Package-on-Package (PoP) technology, delivering performance, form factor & cost benefits in next generation Smartphone processors

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Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure

Cited by 16 publications

References 5 publications

Low cost Cu column fcPoP technology

Low cost Cu column fcPoP technology

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

Advancements in Package-on-Package (PoP) technology, delivering performance, form factor &amp; cost benefits in next generation Smartphone processors

Contact Info

Product

Resources

About

Advancements in Package-on-Package (PoP) technology, delivering performance, form factor & cost benefits in next generation Smartphone processors