CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

Movva, S.; Bezuk, Steve; Bchir, Omar; Shah, Milind; Joshi, Manjusha; Pendse, R.; Ouyang, Eric; Kim, Y C; W, Park S; Lee, H T; Kim, S S; Bae, Hyunil; Na, G C; Lee, K.

doi:10.1109/ectc.2011.5898574

Cited by 25 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, it is also found that the stress in the UBM is the largest in a perpendicular BOL design, which means that the LF bump crack issue can be effectively reduced, but the UBM delamination problem remains an issue in perpendicular BOL devices. Therefore, the use of BOL structures will have better mechanical performance than LF and Cu column bumps in fcFBGA, which is in agreement with the results from our experiment and from the literature [21]- [23].…”

Section: Comparisons and Discussionsupporting

confidence: 94%

Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

Hsieh¹,

Lee²,

Hung³

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

View full text Add to dashboard Cite

Since the employment of copper (Cu) column bump (with lead-free solder cap) interconnect offers flexibility in the aspect ratio, increases the I/O density, and provides the characteristic of fine-pitch bumps in flip-chip technology (less than 150 µm bump pitch), a significant amount of research on Cu column bumps in flip-chip packages has been carried out in recent years. For the implementations of Cu column bumps, the architectures of bump-on-capture (BOC) pad with solder bump on pre-solder and bump-on-lead (BOL) with solder bump on Cu trace are usually adopted in flip-chip packages. For the purpose of realizing the mechanical behaviors for fcFBGA (flipchip fine-pitch ball grid array) with lead-free (LF) bump, Cu column bump, and Cu column bump without (w/o) LF solder cap (Cu column w/o solder cap), this paper presents 3-D finite element analysis (FEA) and compare their warpage and stress responses.The experimental coplanarity measurements for these three types of bumps in fcFBGA are carried out to validate the FEA results. Moreover, the reliability assessment for the underfill selection is further validated with an FEA study. Through validation and simulation, it is observed that the use of an LF bump was better at preventing extreme low-k (ELK) failure and aluminum (Al) pad/underbump metallurgy (UBM) delamination, while the use of Cu column bump with and without a solder cap can avoid presolder crack failure. In addition, because the packaging geometry and material always play important roles in determining mechanical behaviors, identifying the most significant factors that affect the stress and warpage responses is useful if stress and warpage reductions in fcFBGA are required. In order to gain the essential factors in fcFBGA, systematic simulation studies for LF bump, Cu column bump, and BOL are illustrated. The impact levels for the top significant factors that influence the ELK, UBM, and bump stresses as well as the warpage are obtained through systematic simulation studies. Several suggestions for reducing warpage and the critical stresses in fcFBGA with Cu column bumps are recommended. The results show that the stresses in ELK, UBM, and bump in the BOL structure are smaller than those in a BOC structure, demonstrating that the BOL structure provides a reliable fcFBGA package without any ELK damage, UBM delamination, or bump crack issues. The perpendicular BOL orientation in the corner bump area also prevents damage that can be caused by a Cu trace or LF bump. It is believed that the proposed results will provide design guidelines to enhance package reliability and reduce the package cost during the development stage.

show abstract

Section: Comparisons and Discussionsupporting

confidence: 94%

Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

Hsieh¹,

Lee²,

Hung³

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

View full text Add to dashboard Cite

show abstract

“…An NSMD or SMD substrate usually requires a large sized bump pad to connect a bump and a bump pad together. Typically, the size of bump pad is equivalent to the size of a Cu pillar; however, in the BOL substrate, the BOL pad or trace does not require large real estate, equivalent to the size of Cu pillar, resulting in high flexibility in design and significantly increased routing density on the top layer of a substrate [4]. This attribute is a very appealing benefit since it has the potential to reduce the number of layers in the substrate, and in turn, reduces the substrate manufacturing cost.…”

Section: Test Vehicle Descriptionmentioning

confidence: 99%

“…We also noted that bond-on-lead (BOL) substrate is another essential component to enable efficient routing at the substrate level [4]. Thus, this study discusses systematic CPI analysis of GLOBALFOUNDRIES' 20-nm silicon technology with TC-NCP assembly on BOL substrate through collaboration with Amkor Technology.…”

Section: Introductionmentioning

confidence: 99%

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Cho

Gao

Choi

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

The need for high performance and multi-functional devices drove silicon manufacturers to introduce ultra-low dielectric constant (ULK) materials into the back-end-of-line (BEOL) of silicon manufacturing. This innovative technology resulted in performance boost and low RC delay as well as reduced power consumption and cross talk. Although ULK provides electrically improved performance compared to previous generation dielectric materials, it brought significant challenge since the ULK dielectric is a porous and brittle material with inferior material properties.At the same time, advanced packaging flip chip technology is migrating from conventional mass reflow (MR) bonding processing to thermo-compression bonding using non-conductive paste (TC-NCP) to enable higher I/O counts with a smaller form factor. The combination of these trends imposes a significant chip-package interaction (CPI) challenge. Thus CPI qualification of this technology is very crucial to provide the electronics industry the confidence to adopt this technology and prepare for high volume manufacturing.In this paper, Test vehicles with various CPI structures were used to assess the CPI risks of fine pitch flip chip technology with TC-NCP bonding process. To enable efficient routing at the substrate level, a bond-on-lead (BOL) substrate was used. JEDEC Standard CPI reliability test was performed and the data was reviewed electronically and mechanically at each read-out. The test results successfully demonstrate the robustness of GLOBALFOUNDRIES' 20-nm platform flip chip technology with Amkor Technology's TC-NCP bonding process.978-1-4799-8609-5/15/$31.00 ©2015 IEEE

show abstract

“…Therefore, CPI with Cu pillar flip chip packaging becomes very critical in leading edge technology node BEOL development and technology qualification. [1][2][3][4][5][6][7][8][9] In this paper, 20 nm CPI with fine pitch Cu pillar flip chip package is considered. A very systematic research on CPI test vehicle design, BEOL process optimization, ULK material properties characterization, packaging assembly process optimization, reliability tests, and failure analysis was conducted to develop and qualify 20 nm BEOL technology.…”

mentioning

confidence: 99%

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Gao

Smith

Cho

et al. 2014

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.

show abstract

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

Cited by 25 publications

References 3 publications

Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Contact Info

Product

Resources

About