This study investigates techniques to realize self-aligned Indium-Gallium-Zinc Oxide (IGZO) TFTs that are not subject to gate-source/drain misalignment due to overlay error or process bias. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, however this typically requires several microns of gate overlap in order to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. Boron ion implantation has been demonstrated to successfully dope IGZO, resulting in an estimated electron concentration level n ~ 1019 cm-3. Top-gate co-planar TFTs were fabricated using boron implantation to selectively form IGZO:B n+ regions, with the channel region masked by the gate electrode. A novel lithographic strategy to extend this technique to the more traditional bottom-gate staggered TFT configuration has also been explored which utilizes top-side exposure rather than a back-side through-glass exposure, and would enable self-aligned devices on non-transparent substrates. Details of the self-aligned top-gate TFTs, and the top-side exposure lithographic process will be presented.
The focus of this work is on the performance degradation of thermally stressed IGZO TFTs with SiO2 for both the gate dielectric and back-channel passivation material. I-V characteristics of TFTs with bottom-gate (BG) and double-gate (DG) electrode configurations were observed to left-shift and degrade with thermal stress. Experimental results indicate the instability occurs either directly or indirectly due to the influence of H2O within the passivation oxide above the IGZO channel region. An atomic layer deposition (ALD) alumina capping layer applied immediately following the passivation oxide anneal was successful in improving thermal stability. Channel length dependence was observed where longer channel DG devices were more prone to degradation. A hypothesis has been developed with H2O as the expected origin of this phenomenon. Experiments have been specifically designed to establish the feasibility of the proposed mechanism. Furthermore, DG devices which exhibit enhanced thermal stability are presented.
The focus of this work is on the performance dependence of scaled IGZO TFTs with variations in the device structure and semiconductor passivation scheme. TCAD simulation was used to provide insight on the details which establish the limits on electrostatic control. Dielectrics used for the gate and back-channel regions have been adjusted to overcome short-channel effects, along with required modifications in process recipes for PECVD passivation layers, oxygen ambient annealing, and ALD capping material. Scaled devices with channel lengths as small as L = 1 µm have been investigated and evaluated by the electrostatic behavior, and stability when subjected to thermal and bias stress. An optimized process and associated procedural details for scaled devices is presented, along with suggested options for further channel length reduction to submicron dimensions.
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