2019
DOI: 10.1149/09204.0143ecst
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Device Structure and Passivation Options for the Integration of Scaled IGZO TFTs

Abstract: The focus of this work is on the performance dependence of scaled IGZO TFTs with variations in the device structure and semiconductor passivation scheme. TCAD simulation was used to provide insight on the details which establish the limits on electrostatic control. Dielectrics used for the gate and back-channel regions have been adjusted to overcome short-channel effects, along with required modifications in process recipes for PECVD passivation layers, oxygen ambient annealing, and ALD capping material. Scale… Show more

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Cited by 5 publications
(3 citation statements)
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“…The working metal was molybdenum for the gate electrode and source/drain contacts. A passivation anneal was done and a capping layer was added to promote electrical stability; full process details are provided in a previous report (5). Devices were tested using a Lakeshore probe station with a liquid helium cryostat, with transfer characteristic measurements taken from RT to 40 K. The gate bias was swept from -5 to 10 V in 0.1 V increments at select drain voltages (0.1, 1.0, 10 V).…”
Section: Methodsmentioning
confidence: 99%
“…The working metal was molybdenum for the gate electrode and source/drain contacts. A passivation anneal was done and a capping layer was added to promote electrical stability; full process details are provided in a previous report (5). Devices were tested using a Lakeshore probe station with a liquid helium cryostat, with transfer characteristic measurements taken from RT to 40 K. The gate bias was swept from -5 to 10 V in 0.1 V increments at select drain voltages (0.1, 1.0, 10 V).…”
Section: Methodsmentioning
confidence: 99%
“…ITGO devices were compared with IGZO devices with similar dimensions; W/L=24/12 µm, as shown in Figure 7. Process flow and fabrication details of the IGZO device can be found in (9). Note that the characteristic overlay required a 5 V offset for the ITGO device for a consistent subthreshold reference.…”
Section: Itgo Device Characteristicsmentioning
confidence: 99%
“…In general, oxide semiconductor materials conventionally deposited using techniques such as sputtering [10], chemical vapor deposition [11], and sol-gel processes [12] in both research and practice. However, to enhance the performance of capabilities microelectronic components, the semiconductor industry requires the reduction of dimensions with high aspect ratios [13][14][15]. To meet these requirements, atomic layer deposition (ALD) has been proposed.…”
Section: Introductionmentioning
confidence: 99%