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March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST. As March algorithms are well known algorithms for testing embedded RAMS, out of which March Cis known for finding all SAF, SOF, CF. This March C-is used frequently in the industry also. The proposed march algorithm is modified march c-algorithm which uses concurrent technique. Using this modified march c-algorithm the complexity is reduced to 8n as well as the test time is reduced greatly. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. This technique is applied for a memory of size 256x8 and can be extended to any memory size.

In modern VLSI technology the speed and power would always be a trade off. In contrast to that the proposed design gives better technique in improving the speed of computation with high accuracy when compared with conventional adders. And also the implementation gives low power results with better performance. Using the available VLSI design techniques and emerging concepts the high speed low power high accurate (HS-LP-HA) Adder is proposed. The proposed HS-LP-HA adder is capable to give near accurate value along with much low power consumption when compared with conventional adder. Hence also improved power delay product. The proposed HS-LP-HA adder finds its applications in signal processing for communications, control of systems, biomedical signal processing and seismic data processing in all which the minute percentage of error is tolerable

Most of the VLSI applications, such as DSP, image and video processing, and microprocessors use carry select adder (CSLA) for arithmetic functions. From the structure of regular SQRT CSLA, still there is possibility to obtain better design in which optimization of area, power are to be major concentrations along with high speed performance. One of the existing solutions used in SQRT CSLA is replacement of second level RCA by BEC. Though increases the performance, very less percentage of improvement in reduction of area and power dissipation. And also the existing adder with BEC technique is not suitable for low power applications. Hence this paper proposes Special Hardware using Multiplexers (SHM) design in place of second level RCA. It is observed from the results that the area and power dissipation are reduced at comparable percentages with respect to the RCA and BEC techniques. When SHM is used at the second level of second block in 16-bit SQRT CSLA, observed that area is reduced by 13.5% and power dissipation is reduced by 6.4%. This proposed logic is designed in transistor level using 0.12μm technology in the Micro wind tool.

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