Design of High Speed -Low Power-High Accurate (HS-LP-HA) Adder

Parvathi, Muddapu; Vasantha, N.; Prasad, K. Satya

doi:10.7763/ijcce.2013.v2.246

Cited by 3 publications

(2 citation statements)

References 19 publications

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“…Where C load is the load capacitance of the gate, Tcycle is the clock cycle time, E (switching) is the expected number of signal transitions per cycle and V dd is the supply voltage [7].…”

Section: Introductionmentioning

confidence: 99%

Efficient carry select adder using 0.12µm technology for low power applications

Reddy¹,

Parvathi²

2013

2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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Most of the VLSI applications, such as DSP, image and video processing, and microprocessors use carry select adder (CSLA) for arithmetic functions. From the structure of regular SQRT CSLA, still there is possibility to obtain better design in which optimization of area, power are to be major concentrations along with high speed performance. One of the existing solutions used in SQRT CSLA is replacement of second level RCA by BEC. Though increases the performance, very less percentage of improvement in reduction of area and power dissipation. And also the existing adder with BEC technique is not suitable for low power applications. Hence this paper proposes Special Hardware using Multiplexers (SHM) design in place of second level RCA. It is observed from the results that the area and power dissipation are reduced at comparable percentages with respect to the RCA and BEC techniques. When SHM is used at the second level of second block in 16-bit SQRT CSLA, observed that area is reduced by 13.5% and power dissipation is reduced by 6.4%. This proposed logic is designed in transistor level using 0.12μm technology in the Micro wind tool.

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“…Where C load is the load capacitance of the gate, Tcycle is the clock cycle time, E (switching) is the expected number of signal transitions per cycle and V dd is the supply voltage [7].…”

Section: Introductionmentioning

confidence: 99%

Efficient carry select adder using 0.12µm technology for low power applications

Reddy¹,

Parvathi²

2013

2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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“…One way to increase the speed in BIST operation is by using efficient adder circuits which are used as address generators. One method of achieving faster adders was proposed in [13 ]. Because adders will generate the input sequence for the decoder through which address sequence will be generated.…”

Section: Modified March C-algorithm and Proposed Hardware Implementationmentioning

confidence: 99%

Modified March C-With Concurrency in Testing for Embedded Memory Applications

Parvathi

2012

VLSICS

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March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST. As March algorithms are well known algorithms for testing embedded RAMS, out of which March Cis known for finding all SAF, SOF, CF. This March C-is used frequently in the industry also. The proposed march algorithm is modified march c-algorithm which uses concurrent technique. Using this modified march c-algorithm the complexity is reduced to 8n as well as the test time is reduced greatly. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. This technique is applied for a memory of size 256x8 and can be extended to any memory size.

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