Single-ISA heterogeneous (also known as asymmetric) multicore processors offer significant advantages over homogenous multicores in terms of both power and performance. Power-efficient cores can be paired with higherperformance cores to achieve advantageous power/performance tradeoffs. Unfortunately, such processors also create unique challenges in effective mapping of processes to cores. The greater the diversity of cores, the more complex this problem becomes. Previous scheduling approaches sample performance while permuting the schedule across each type of core each time a change in application behavior is detected. However, approaches that require frequent sampling of the performance of threads (or combinations of threads) on each core may be impractical. We propose scheduling threads on a heterogeneous multicore processor using not just the detection of a change in program behavior or phase, but instead an identification and recording of these phase behaviors. We highlight the correlation between the execution phases of an application and the performance of those phases on any particular core type. We present mechanisms that exploit this correlation between program phases and appropriate scheduling decisions and demonstrate near optimal mapping of thread segments to processor cores can be done without frequently sampling the performance of each thread on each processor core type.
Complex number arithmetic computations are one of the key arithmetic components in modern digital communication and optical systems. Complex number multiplication and complex number inner-product play a unique role in these applications. In this paper, a complex-number multiplier and complex-number inner-product processor based on a Redundant Binary (RB) representation are presented. This work is an extension of a previous real fied-point inner-product hardware design [l]. With the proposed algorithms. the complex number multiplication is reduced to parallel RE multiplications, and the complex number inner-product is produced using a RE addition tree.This proposed inner-product processor can be reconfigured or conpolled to perform dyerent computations such as inner-product processing or parallel multiplies for real andor complex numbers. The design results. not only in simplified arithmetic operations, but also in a highly parallel and simple architecture when compared with other methods.
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