High-speed complex number multiplier and inner-product processor

Tull, Monte P.; Wang, Guoping; Özaydın, Murad

doi:10.1109/mwscas.2002.1187121

Cited by 12 publications

(5 citation statements)

References 9 publications

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“…The conventional method of complex number multiplication requires four real multipliers and two real additions. Note that the Gauss complex multiplication algorithm [57] requires only three real multiplication and five real additions. Therefore, a 4-point FFT digital PAF beamformer requires multipliers per element.…”

Section: B Computational Complexitymentioning

confidence: 99%

Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications

Joshi

Madanayake

Adikari

et al. 2012

IEEE Trans. VLSI Syst.

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A broadband digital beamforming algorithm is proposed for directional filtering of temporally-broadband bandpass space-time plane-waves at radio frequencies (RFs). The enhancement of desired waves, as well as rejection of undesired interfering plane-waves, is simulated. A systolic-and wavefront-array architecture is proposed for the real-time implementation of second-order spatially-bandpass (SBP) 2-D infinite impulse response (IIR) beam filters having potential applications in broadband beamforming of temporally down-converted RF signals. The higher speed of operation and potentially reduced power consumption of the asynchronous architecture of wavefront-array processors (WAPs) in comparison to the conventional synchronous hardware has emerging applications in radio-astronomy, radar, navigation, space science, cognitive radio, and wireless communications. Further, the bit error rate (BER) performance improvement along with the reduced computational complexity of the 2-D IIR SBP frequency-planar digital filter over digital phased array feed (PAF) beamformer is provided. A nominal BER versus signal-to-interference ratio (SIR) gain of 10-16 dB compared to case where beamforming is not applied, and a gain of 2-3 dB at approximately half the number of parallel multipliers to digital PAF, are observed. The results of application-specific integrated circuit (ASIC) synthesis of the digital filter designs are also presented.Index Terms-Array processors, bit error rate (BER), digital phased array feed (PAF), field-programmable gate array (FPGA), multidimensional digital filters, spatial modulation, systolic, wavefront, wireless.

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Section: B Computational Complexitymentioning

confidence: 99%

Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications

Joshi

Madanayake

Adikari

et al. 2012

IEEE Trans. VLSI Syst.

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“…Finally, we estimate the computational cost of the beamformer with a recursive updating of the Cholesky factorization. As follows from the algorithm description on the step 1 -step 4, all computations contain only vector operations, such as inner and outer products, which can easy implemented with inner-product processors [26]. The cost of step 2 is essentially zero operations; of step 3 is ; of step 4 is operations.…”

Section: Recursive Implementation With Cholesky Factorizationmentioning

confidence: 99%

“…Let us consider the product (26) The matrix product in (26) coincides with the diagonal loading matrix that was introduced in (11). On the other hand (27) where is an orthonormal Householder matrix, and .…”

Section: A Householder Transform Of Modified Input Matrixmentioning

confidence: 99%

“…On the other hand (27) where is an orthonormal Householder matrix, and . From (26), (27) follows that the resulting triangular matrix computed by either the HT over the matrix or the Cholesky factorization over the matrix is the same, if the round-off errors due to finite word-length are ignored. However, computing with HT is preferable, because HT outperforms the Cholesky method when the finite word precision computing is used.…”

Section: A Householder Transform Of Modified Input Matrixmentioning

confidence: 99%

“…It gives some computational savings when . Furthermore, it is suitable for highly parallel implementations with vector processors based on FPGAs or DSPs [26], [31]. The corresponding computational costs are the VCD-MVDR beamformer is , the VHT-MVDR beamformer is .…”

Section: Relative Computational Cost and Numerical Performance Testmentioning

confidence: 99%

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SMI-MVDR Beamformer Implementations for Large Antenna Array and Small Sample Size

Zaharov

Teixeira

2008

IEEE Trans. Circuits Syst. I

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Two online implementations of the sample matrix inversion minimum variance distortionless response (SMI-MVDR) antenna array beamformer, based on recursive updating of the diagonal loading triangular matrix decomposition, are presented. The first proposed beamformer uses the Cholesky factorization recursive updating of the matrix whose dimension is increasing. The second beamformer uses the Householder transform (HT) recursive updating of the modified input data matrix. The proposed implementations consist primarily of vector operations, that is, they are suitable for parallel implementations with FPGAs or DSPs. The computational cost of the proposed beamforming algorithms is O(Nk), where N is the number of antenna array elements, and k is the number of processing snapshots. The proposed implementations are especially useful for large antenna array applications, where the number of available snapshots does not exceed the number of the array antenna elements. The simulation result shows that the numerical performance of the proposed beamformers is superior, relative to the conventional recursive MVDR beamformer implementation.

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Redundant binary based fixed-point divider

Bennis¹,

Tull²

Canadian Conference on Electrical and Computer Engineering, 2005.

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High-speed complex number multiplier and inner-product processor

Cited by 12 publications

References 9 publications

Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications

Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications

SMI-MVDR Beamformer Implementations for Large Antenna Array and Small Sample Size

Redundant binary based fixed-point divider

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