The quantum-dot cellular automata technology has great attention in nanoscale digital circuits design due to its high-speed and high-dense. Shift registers play vital role in digital circuits design. So, efficient implementation of shift register circuits in this technology is in the focal point of researches in digital circuits design. In this study, new structures are proposed for the shift register circuits in single layer, three layers and five layers based on inherent quantum-dot cellular automata clock. The QCADesigner tool version 2.0.3 is employed for simulation and verification of functionality of the proposed structures for the serial-input-serial-output shift register circuits. The results demonstrate that the developed 3-bit, 4-bit and 5-bit coplanar shift register circuits require 32, 44 and 56 cells, respectively. The comparison results demonstrate that the developed circuits provide advantages compared to other circuits in terms of area, cell count, clock cycles and cost.
Summary
The QCA technology is a promising emerging technology at nano‐scale for replacing CMOS technology. Shift register has a vital role in communication networks and digital electronic circuits that are the main components of integrated circuits and memory. In this study, novel and efficient delay circuit (pseudo‐D‐Latch) is designed. Then, 3‐, 4‐, and 5‐bit SISO QCA shift register architectures are developed and evaluated in single layer, 3‐layer and 5‐layer using the designed delay circuit. The designed architectures are evaluated using QCADesigner‐E tool version 2.2. The results demonstrate that the pseudo‐D‐Latch circuit contains 17 cells and 0.01 μm2 area. The 3‐, 4‐, and 5‐bit single layer SISO QCA shift register architecture contains 63 (0.05 μm2), 85 (0.66 μm2), and 107 (0.08 μm2) cells (area), respectively. The 3‐ and 4‐bit 3‐layer SISO QCA shift register architecture contains 63 (0.03 μm2) and 84 (0.03 μm2) cells (area), respectively. The 3‐ and 5‐bit 5‐layer SISO QCA shift register architecture contains 62 (0.02 μm2) and 105 (0.032 μm2) cells (area), respectively. These results show that the designed QCA architectures provide improvements compared with other SISO QCA architectures.
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