Towards Multilayer QCA SISO Shift Register Based on Efficient D-FF Circuits

Divshali, Mojtaba Niknezhad; Rezai, Abdalhossein; Karimi, Asghar

doi:10.1007/s10773-018-3846-8

Cited by 42 publications

(38 citation statements)

References 22 publications

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“…QCA technology is a promising technology for implementation of digital circuits in nano-scale [1][2][3][4][5][6]. The comparator circuits play important role in digital circuits [9][10][11][12][16][17][18].…”

Section: Discussionmentioning

confidence: 99%

“…The Quantum-dot Cellular Automata (QCA) technology is an emerging and promising technology to these issues at nano-scale [1]. The basic element in this technology is a square cell that has two free electrons in four dots [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. The QCA cell is a building block for constructing QCA gates [1][2][3][4][5][6][7][8][9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

“…The QCA cell is a building block for constructing QCA gates [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. There are three basic gates in this technology: inverter gate, majority (M) gate, and XOR gate [3][4]. These gates are building blocks for constructing the logic circuits such as QCA multiplexers [5,7], QCA full address [1-3, 6, 8] and QCA comparators [9][10][11][12][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

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Design of efficient coplanar 1-bit comparator circuit in QCA technology

2019

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QCA technology is an emerging and promising technology for implementation of digital circuits in nano-scale. The comparator circuits play an important role in digital circuits. In this work, a new and efficient coplanar 1-bit comparator circuit is proposed and evaluated in the QCA technology. The designed coplanar 1-bit QCA comparator circuit is constructed based on majority gate, XNOR gate and inverter gate that are designed carefully. The functionality of the designed coplanar 1-bit QCA comparator circuit is verified by using QCADesigner version 2.0.3. The obtained results indicate that the designed 1-bit QCA comparator circuit requires 0.03 µm 2 area and 38 QCA cells. It also has 0.5 clock cycles delay. The comparison demonstrates that the designed QCA comparator circuit provides improvements in comparison with other QCA comparator circuits in terms of effective area, cell count, and delay as well as cost.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of efficient coplanar 1-bit comparator circuit in QCA technology

2019

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“…There is relatively low‐energy dissipation since there is negligible energy dissipation during the propagation and state transition in QCA 4–6 . QCA technology is being explored exhaustively, and various logics such as adders, 7–14 code converters, 15–18 sequential circuits, 19–23 and memories 24–27 are being proposed for various applications. One such area considered of application is secure transmission of information.…”

Section: Introductionmentioning

confidence: 99%

Design of quantum‐dot cellular automata technology based cost‐efficient polar encoder for nanocommunication systems

Ahmed

Naz

Bhat

2020

Int J Communication

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SummaryIn the current digital era, there is a need of secure and efficient nanocommunication systems with ultralow power consumption. One technology that can be used for designing these systems is the quantum‐dot cellular automata (QCA). In the nanoregime, QCA is able to operate with higher speed and lower power dissipation compared with complementary metal oxide semiconductor technology. This work explores the applicability and feasibility of polar encoders, which felicitates reliable data communication with reduced probability of error, in nanocommunication systems. In this paper, (8,4) polar encoder is proposed in QCA technology. The proposed design is a single‐layer structure designed using only 600 cells consuming cell area of 0.1944 μm2 and total area of 0.7225 μm2 with a latency of 3.75 clock cycles, which results in a cost of 10.16. Based on the performance comparison, it is observed that the proposed design is cost‐efficient and achieves improvement up to 49.49% in terms of number of cells and area consumption, 40% improvement in latency, and 86.42% improvement in terms of cost compared with the only design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. Hence, the proposed designs can be efficiently utilized in nanocommunication systems requiring minimal area and ultralow power consumption.

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“…Thereby they started to minimize the area and power consumption. Today area utilization, power dissipation [2][3][4] becomes an important design issue in VLSI circuits .This tends to pay attention on power dissipation and number of transistors. When it comes to portability of devices, power dissipation is an unavoidable constraint [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Efficient 8-Bit SIPO Shift Register

Kakde¹,

S²,

Kamble³

et al. 2020

JUSST

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Area and power are main design constraints in analog and digital circuits. In this paper, a low-power 8-bit shift register is implemented by using true phase single clock (TSPC) D- flip flop which is based on single clock and two clocked transistors. The proposed design successfully solves the long discharge path problem which is bound to occur in conventional type of D-Flip Flop. This paper describes 8 bit serial in parallel out (SIPO) shift register using True Single-Phase Clock(TSPC) technique which reduces an area in terms of transistor count by 85.29%.

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Towards Multilayer QCA SISO Shift Register Based on Efficient D-FF Circuits

Cited by 42 publications

References 22 publications

Design of efficient coplanar 1-bit comparator circuit in QCA technology

Design of efficient coplanar 1-bit comparator circuit in QCA technology

Design of quantum‐dot cellular automata technology based cost‐efficient polar encoder for nanocommunication systems

Design and Implementation of Efficient 8-Bit SIPO Shift Register

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