This work focuses on characterizing the performance of the 3D TSVs under high speed transient simulation, which could potentially evaluate and verify the electrical models for these vertical connections. A Gunning Transceiver Logic ( GTL) I/O on-chip test IC and a CML/Thermal test IC has been designed and sent for fabrication using the 3D FDSOI CMOS technology. The GTL I/O circuits are used to inject different data patterns at different frequencies across different tiers. A control MUX with Tri-state buffers and control logic can be used to switch between different I/O GTL drivers at different tiers. The GTL I/O test IC is dedicated to measure the NEXT/FEXT crosstalk between vertical connections by firing high speed signals from different tiers. The datadependent-Jitter (DDJ) will be characterized by observing the eye diagram for a random and different data patterns.CML I/O circuits were designed to characterize high speed differential transmission, especially, the performance of high current buffers in the three tiered-system implementation. Differential signals were used to test the performance of through-silicon vias (TSV) and interconnect as the signals transmit from IC tier-to-tier. In addition, temperature sensors were integrated in order to model the 3D thermal performance as affected by the I/O drivers.
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