A typical semiconductor fabrication process contains 300 to 1000 steps and its variation depends on the product complexity. Most of the processes are re-entrance to same equipments especially at photolithography, etching, implanter, film deposition, chemical mechanical polishing (CMP) and cleaning. For example, photolithography steps for island, poly, and contact module will be processed at same equipment. Another complication is that the equipment types are different from one to another resulting in different approach for cycle time calculation, difference in availability and efficiency. The objective of this paper is to establish capacity indices to guide for monthly output in semiconductor fabrication facilities. The approach in this paper is using the waterfall chart for individual process and equipment types. Data extraction is being done through reporting systems of Advance Productivity Family (APF), an industrial standard software for data collection that is integrated with individual equipment and product processing historical data. The data was then analyzed using JMP to check for sanity. Results were used to develop capacity indices, which are wafer per hour (wph), manufacturing efficiency, and equipment availability. All these information will be later used to develop the final capacity figure. The final capacity number will then be used to guide the planning team to schedule product combination that will achieve monthly and quarterly wafer shipment goal to customers. This approach reached accuracy of 99% compared to actual throughput. In conclusion, this approach helps the company to provide planning guidelines in meeting the financial goals.Index Terms-Advance Productivity Family (APF), Chemical mechanical polishing (CMP), Work In progress (WIP), wafer per hour (wph)
PurposeThis research proposes weighted grey relational analysis (WGRA) method to evaluate the performance of 325 multilevel dispatching rules in the wafer fabrication process.Design/methodology/approachThe research methodology involves multilevel dispatching rule generation, simulations, WGRA and result analysis. A complete permutation of multilevel dispatching rules, including the partial orders, is generated from five basic rules. Performance measures include cycle time, move, tool idling and queue time. The simulation model and data are obtained from a wafer fab in Malaysia. Two seasons varying in customer orders and objective weights are defined. Finally, to benchmark performance and investigate the effect of varying values of coefficient, the models are compared against TOPSIS and VIKOR.FindingsResults show that the seasons prefer different multilevel dispatching rules. In Normal season, the ideal first basic dispatching rule is critical ratio (CR) and CR followed by shortest processing time (SPT) is the best precedence pairing. In Peak season, the superiority of the rule no longer heavily relies on the first basic rule but rather depends on the combination of tiebreaker rules and on-time delivery (OTD) followed by CR is considered the best precedence pairing. Compared to VIKOR and TOPSIS, WGRA generates more stable rankings in this study. The performance of multicriteria decision-making (MCDM) methods is influenced by the data variability, as a higher variability produces a much consistent ranking.Research limitations/implicationsAs research implications, the application illustrates the effectiveness and practicality of the WGRA model in analyzing multilevel dispatching rules, considering the complexity of the semiconductor wafer fabrication system. The methodology is useful for researchers wishing to integrate MCDM model into multilevel dispatching rules. The limitation of the research is that the results were obtained from a simulation model. Also, the rules, criteria and weights assigned in WGRA were decided by the management. Lastly, the distinguishing coefficient is fixed at 0.5 and the effect to the ranking requires further study.Originality/valueThe research is the first deployment WGRA in ranking multilevel dispatching rules. Multilevel dispatching rules are rarely studied in scheduling research although studies show that the tiebreakers affect the performances of the dispatching rules. The scheduling reflects the characteristics of wafer fabrication and general job shop, such as threshold and look-ahead policies.
Production planning and control in semiconductor manufacturing is complicated by high-level of re-entrant. Job batching is commonly used to reduce required setup time and maximize workstation utilization. New research promotes CONWIP in pull production systems, while limiting overall work-in-process. However, the implications of batching on CONWIP systems have not been well studied. This paper describes a series of simulation studies and adopted ANOVA and response surface methodology to investigate the effects and relationship of batching on different numbers of CONWIP cards, demand composition, re-entrant, and setup times. Simulation results show that all batching systems exhibited a high number of CONWIP cards and low job mix, total layers, and setup times when the lowest average flow time as well as the highest throughput level and workstation utilization are achieved. The overall result reveals that batching systems outperform non-batching systems in the simulation model of a CONWIP production control system in semiconductor manufacturing.
This research is to investigate simulation modeling method for semiconductor fabrication factories (FAB) that known for complex manufacturing operation from various the literatures. This paper covers literatures from various publications since past 10 years. The significant simulation model used in common and semiconductor fabrication will be selected for evaluation in semiconductor fabrication manufacturing operation scenario with high mixed. Depends to the products mixed configuration, cycle time to complete semiconductor fabrication will take 60 to 90 days. The longer period needed due to wafer process required 300 to 1000 steps, process re-entrance to similar equipment more than 30% of the total steps further increase the complexity with many configuration due to setup changes. The simulation also needs to configure for process queue time, process dedication, several of difference for equipment configuration, capability and capacity. Primary simulation techniques reviewed in this analysis are discrete event, petri-net, gaming, virtual, intelligent, monte carlo and hybrid to understand individual strength and common usage in the market. This research summarized the highest usage, most uses and compatibility in similar operation for semiconductor fabrication. In summary, the research concluded DES is the most suitable technique for simulating FAB operation because of its nature of queuing and leaving concept that fits and resulted to 95% accuracy for WIP forecasting.
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