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Aggregated amyloid beta (Aβ) peptides are believed to play a decisive role in the pathology of Alzheimer's disease (AD). Previous evidence suggested that exercise contributes to the improvement of cognitive decline and slows down pathogenesis of AD; however, the exact mechanisms for this have not been fully understood. Here, we evaluated the effect of a 4-week moderate treadmill exercise on spatial memory via central and peripheral Aβ clearance mechanisms following developed AD-like neuropathology induced by intra-hippocampal Aβ injection in male Wistar rats. We found Aβ-treated animals showed spatial learning and memory impairment which was accompanied by increased levels of amyloid plaque load and soluble Aβ (sAβ), decreased mRNA and protein expression of neprilysin (NEP), insulin degrading enzyme (IDE) and low-density lipoprotein receptor-related protein-1 (LRP-1) in the hippocampus. Aβ-treated animals also exhibited a higher level of sAβ and a lower level of soluble LRP-1 (sLRP-1) in plasma, as well as a decreased level of LRP-1 mRNA and protein content in the liver. However, exercise training improved the spatial learning and memory deficits, reduced both plaque load and sAβ levels, and up-regulated expression of NEP, IDE, and LRP-1 in the hippocampus of Aβ-treated animals. Aβ-treated animals subjected to treadmill exercise also revealed decreased levels of sAβ and increased levels of sLRP-1 in plasma, as well as increased levels of LRP-1 mRNA and protein in the liver. In conclusion, our findings suggest that exercise-induced improvement in both of central and peripheral Aβ clearance are likely involved in ameliorating spatial learning and memory deficits in an animal model of AD. Future studies need to determine their relative contribution.

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In this paper, a new ultra-low-power voltage reference based on a two-stage, all-pMOS topology operating in the subthreshold region is proposed to uniquely meet the pW-power range power consumption requirements of emerging Internet-of-Things applications without significantly compromising the temperature coefficient (TC) and the line sensitivity (LS) performance. The proposed circuit consists of the LS regulator, TC corrector, and TC trimming sections. Based on post-layout Monte Carlo simulations in 180-nm CMOS, the proposed circuit operates with 0.8-to 2.4-V supply potential and generates a reference voltage of 206 mV with a process spread of 7.8%, achieving an average calibrated TC of 4.4 ppm/ C in the temperature range of À20 C to 80 C, and an average LS of 51.5 ppm/V with a power consumption of 25.9 pW at 25 C (469.1 pW at 80 C).