No abstract
The ever growing volume of backplane communications pushes the data rate toward 20Gb/s for the next-generation transceivers. Over the years, chip designers have been seeking different data formats to overcome the loss of electrical channels. Among the existing solutions, duobinary signaling manifests itself in bandwidth efficiency as (1) its spectrum occupies only half as wide as that of NRZ data; (2) it incorporates the intrinsic roll-off bandwidth of the channel as part of the desired response. The design and experimental verification of a fully-integrated duobinary transceiver in 90nm CMOS is described. The transceiver achieves 20Gb/s error-free transmission over a 40cm Rogers and a 10cm FR4 channels. Figure 5.3.1 shows the conceptual illustration of the transceiver.Since the duobinary signaling is defined as the sum of the present bit and the previous one, it possesses a transfer function of 1+z -1 , i.e., the spectrum of a duobinary signal resembles that of a PAM4 with the same data rate. In circuit design, the pre-emphasis trims or reshapes the low-pass response of the channel such that the overall transfer function approximates the first lobe of it, absorbing significant amount of channel loss and relaxing the boost requirement. The decoder 1/( 1+z -1 ) is usually realized as a precoder at the transmit side to avoid the devastating and unrecoverable error propagation. The duobinary signal at far end y 2 is converted back to NRZ data by a 3-level (1.58-bits) ADC with only the LSB taken out. Note that no data information is lost is such a single-bit system. The duobinary transceiver is compatible with regular NRZ systems if one bypass the precoder and degenerate the ADC to 1 bit. Figure 5.3.2 depicts the transmitter design. The conventional precoder requires that the XOR gate delay and the ΔT must comprise exactly one bit period, posing difficult challenges at high speed even with a clock-driven delay cell. To remedy this, the precoder is realized as an AND gate followed by a ÷2 circuit [1]. The output toggles whenever a data ONE arrives, leading to the following operation:This structure allows a clock skew margin as wide as 180°, substantially relaxing the phase relationship by breaking the loop. The FFE still proves useful in duobinary, with the exception that a single pulse is expected to generate 2 consecutive bits at the far end. In other words, the coefficients α -1~α2 can be calculated by solving the 4×4 matrix with a response of [0 1/2 1/2 0]. In this prototype, all the blocks are implemented as currentmode logic to increase speed, and α 2 (and the corresponding flipflop) is omitted due to its insignificant contribution.While looking simple and feasible, the ADC-based receiver in Fig. 5.3.1 suffers from a number of drawbacks. The linearity and input common mode require accurate reference voltages (V TH,H and V TH,L ), otherwise the signal integrity degrades. In addition, the sampling in the ADC needs direct clock recovery from the 3-level duobinary input, complicating the circuit design. To overcome...
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