A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

Chen, Ming-Shuan; Shih, Yu-Nan; Lin, Chen-Lun; Hung, Hao-Wei; Lee, Jri

doi:10.1109/jssc.2011.2176635

Cited by 73 publications

(22 citation statements)

References 20 publications

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“…Indeed, the operational bandwidth of a bang-bang CDR is commensurate with that of a flipflop (sampler). However, previous work in [20] demonstrates that a flipflop can hardly operate beyond 32 Gb/s. In other words, only sub-rate architecture is doable even at 40 nm CMOS.…”

Section: B Receivermentioning

confidence: 98%

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Lee

Chiang

Peng

et al. 2015

IEEE J. Solid-State Circuits

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116

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This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data. The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data. NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner. NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data. All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE.Index Terms-Clock and data recovery (CDR), equalizer, highspeed serial link, NRZ, PAM4, phase-locked loop (PLL), SerDes, transceiver (TRX).

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Section: B Receivermentioning

confidence: 98%

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Lee

Chiang

Peng

et al. 2015

IEEE J. Solid-State Circuits

Self Cite

116

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“…In high-speed data link, as the data-rate goes up to several tens of Gb/s, the transmission line techniques become viable and attractive for high-performance circuit design. One function of the transmission line in high-speed data link is for generating timing delay while maintaining the characteristic impedance of the delay line to match with the terminating resistor [7][8]. By using passive transmission line instead of active timing delay circuit, the power consumption is reduced.…”

Section: Artificial Lc Transmission Linementioning

confidence: 99%

“…As long as the signal frequency is fairly below the cut-off frequency, the artificial LC transmission line could be treated as a virtual continuous transmission line and the broadband signal dispersion caused by different phase shifting of variant frequency components can also be well controlled [8].…”

Section: Artificial Lc Transmission Linementioning

confidence: 99%

A low-power 28 Gb/s CDR using artificial lc transmission line technique in 65 nm CMOS

Guo

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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This paper presents a low-power 28 Gb/s PLLbased clock and data recovery circuit in 65 nm CMOS technology. The artificial LC transmission line technique is proposed to be used in the full-rate bang-bang phase detector to reduce the number of D-latches and save power consumption by 42.8% compared with the conventional phase detector design. By using the transmission line technique, the retiming circuit is merged into the phase detector, which further saves power of the data retiming circuit. The compact phase detector with built-in retiming circuit also alleviates the capacitive loading of and saves corresponding power consumed by the clock buffer. In addition, the artificial LC transmission line is proposed to be used in the clock buffer to drive the distributed capacitive loads presented by separate D-latch and save power consumption by 50% compared with the conventional inductive peaking clock buffer. The total power consumption of the CDR is 35 mW from a 1.1 V supply. Keywords-Clock and data recovery (CDR); low-power; transmission line; phase-locked loop (PLL)

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“…At the receiver side, the 1:2 DEMUX uses the half-rate clock to halve the input data rate of . Besides, the multi-phase clock further slows down the received data with 1: DEMUX ( ) [4]. In this paper, we focus on data converting for the maximum data transmission rate to realize a 2:1 MUX in the transmitter and a 1:2 DEMUX in the receiver.…”

Section: Introductionmentioning

confidence: 99%

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

Chen

Chang

2015

IEEE Trans. Circuits Syst. I

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This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred milliwatts power consumption.

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A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

Cited by 73 publications

References 20 publications

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

A low-power 28 Gb/s CDR using artificial lc transmission line technique in 65 nm CMOS

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

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