-This paper presents a 3-wire SPI protocol chip design for application-specific integrated circuit (ASIC) and fieldprogrammable gate array (FPGA). It is the first study to realize SPI protocol by VLSI and FPGA technique for testing and verifying SPI protocol. The FPGA device is used as master device to control the ASIC design which is be as slave device. Moreover, the functions of SPI protocol is successfully worked by testing with oscilloscope. The ASIC design of this work contained 5.1 K gate counts and consumed 19 mW by using a TSMC 0.18 μm CMOS process. This work develops advanced VLSI architecture with only four pads (including system clock in ASIC design).
In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.
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