A 3-wire SPI Protocol Chip Design with Application-Specific Integrated Circuit (ASIC) and FPGA Verification

Abstract

-This paper presents a 3-wire SPI protocol chip design for application-specific integrated circuit (ASIC) and fieldprogrammable gate array (FPGA). It is the first study to realize SPI protocol by VLSI and FPGA technique for testing and verifying SPI protocol. The FPGA device is used as master device to control the ASIC design which is be as slave device. Moreover, the functions of SPI protocol is successfully worked by testing with oscilloscope. The ASIC design of this work contained 5.1 K gate counts and consumed 19 mW by using a TSMC 0.18 μm CMOS process. This work develops advanced VLSI architecture with only four pads (including system clock in ASIC design).

A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

“…The gate count and area of the chip are 5.07 K and 692 × 655 µm 2 , respectively. Compared to the three-wire SPI protocol design in [17], the proposed protocol has a core gate count of only 0.63 K and the power consumption is 12 mW which is lower than in [17] which had 19 mW. The proposed design successfully implemented a two-wire communication with a lower gate count and power consumption which can be used and be beneficial in the oscillator controller with its low cost and low power features.…”

“…To support a full-duplex mode, the SPI protocol is used with a faster transmission speed than the I 2 C protocol as mentioned in [14]. Considering the chip area and cost, [17] successfully realized a three-wire SPI protocol on ASIC as shown in Figure 5. The data line was named SDO for the master device to transmit data to a slave device, and SDI for the master device to receive data from a slave device.…”

“…Although the two data lines combined to one data line is an effective way to reduce the number of interface lines, in a synchronous interface, one data line cannot transmit and receive data at the same time. Therefore, the design [17] does not support the full-duplex mode for data communication and data transmission speed is limited to only one data line. Figure 6 shows the low-cost three-wire SPI protocol design realized on an FPGA and an ASIC system where FPGA is used as a master device and the ASIC as a slave device.…”

“…Consequently, it is necessary to develop a new approach to maintain the benefits of speed and overcome the bus problem as well. The study in [17] presented a three-wire SPI protocol and implemented it using a TSMC 0.18 µm CMOS process with low power and low chip area. With the bidirectional data channel technique, the proposed low power and low chip area three-wire SPI design was successfully verified on an application-specific integrated circuit (ASIC) system and on a field-programmable gate array (FPGA).…”

“…Therefore, this paper proposes a novel low-power synchronous preamble data line protocol interface for the oscillator control application that uses a synchronous technique to reduce the gate count instead of the asynchronous interface. For verification, [17][18][19][20][21][22][23] provided efficient ways to design and test an SPI protocol while [17,[21][22][23] showed that an FPGA is an effective way to implement the verification environment. The proposed protocol is realized to a circuit design using the TSMC 0.18 µm CMOS process and was successfully verified on FPGA and ASIC systems.…”