The continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of > 1.5× independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of > 4×, > 7×, and > 8× for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12×.
Increases in X-ray brightness from synchrotron light sources lead to a requirement for higher frame rates from hybrid pixel array detectors (HPADs), while also favoring charge integration over photon counting. However, transfer of the full uncompressed data will begin to constrain detector design, as well as limit the achievable continuous frame rate. Here a data compression scheme that is easy to implement in a HPAD's application-specific integrated circuit (ASIC) is described, and how different degrees of compression affect image quality in ptychography, a commonly employed coherent imaging method, is examined. Using adaptive encoding quantization, it is shown in simulations that one can digitize signals up to 16383 photons per pixel (corresponding to 14 bits of information) using only 8 or 9 bits for data transfer, with negligible effect on the reconstructed image.
Today, most X-ray pixel detectors used at light sources
transmit raw pixel data off the detector ASIC. With the availability
of more advanced ASIC technology nodes for scientific application,
more digital functionalities from the computing domains (e.g.,
compression) can be integrated directly into a detector ASIC to
increase data velocity. In this paper, we describe a lightweight,
user-configurable detector ASIC digital architecture with on-chip
compression which can be implemented in 130 nm technologies in a
reasonable area on the ASIC periphery. In addition, we present a
design to efficiently handle the variable data from the stream of
parallel compressors. The architecture includes user-selectable
lossy and lossless compression blocks. The impact of lossy
compression algorithms is evaluated on simulated and experimental
X-ray ptychography datasets. This architecture is a practical
approach to increase pixel detector frame rates towards the
continuous 1 MHz regime for not only coherent imaging techniques
such as ptychography, but also for other diffraction techniques at
X-ray light sources.
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