A Hardware Co-design Workflow for Scientific Instruments at the Edge

Yoshii, Kazutomo; Sankaran, Rajesh; Strempfer, Sebastian; Levental, Maksim; Hammer, Mike; Miceli, Antonino

doi:10.1007/978-3-030-96498-6_12

Cited by 2 publications

(2 citation statements)

References 29 publications

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“…The reduction stage takes the output of multiple parallel encoders, consisting of both constant and variable-length data and turns it into a single continuous variable-length output. The implementation and resource optimization strategy is described in our previous work [34]. The packing module then combines this variable-length data across clock cycles until a fixed number of bits has accumulated.…”

Section: Coalescing Modulesmentioning

confidence: 99%

A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging

Strempfer¹,

Zhou²,

Yoshii³

et al. 2022

J. Inst.

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Today, most X-ray pixel detectors used at light sources transmit raw pixel data off the detector ASIC. With the availability of more advanced ASIC technology nodes for scientific application, more digital functionalities from the computing domains (e.g., compression) can be integrated directly into a detector ASIC to increase data velocity. In this paper, we describe a lightweight, user-configurable detector ASIC digital architecture with on-chip compression which can be implemented in 130 nm technologies in a reasonable area on the ASIC periphery. In addition, we present a design to efficiently handle the variable data from the stream of parallel compressors. The architecture includes user-selectable lossy and lossless compression blocks. The impact of lossy compression algorithms is evaluated on simulated and experimental X-ray ptychography datasets. This architecture is a practical approach to increase pixel detector frame rates towards the continuous 1 MHz regime for not only coherent imaging techniques such as ptychography, but also for other diffraction techniques at X-ray light sources.

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Section: Coalescing Modulesmentioning

confidence: 99%

A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging

Strempfer¹,

Zhou²,

Yoshii³

et al. 2022

J. Inst.

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show abstract

“…Our proposed solution is realized by means of hardware specialization and can also be an essential component in other specialized hardware designs if we provide our design as a reusable hardware library. In our recent study [11], we discussed the importance of streaming computing at the edge of scientific instruments along with the challenges and opportunities within hardware specialization methodology. This included several usage examples of opensource hardware design tools such as Chisel and Yosys [12].…”

Section: Introductionmentioning

confidence: 99%

Designing a Streaming Data Coalescing Architecture for Scientific Detector ASICs with Variable Data Velocity

Strempfer¹,

Yoshii²,

Hammer³

et al. 2021

Preprint

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Scientific detectors are a key technological enabler for many disciplines. Application-specific integrated circuits (ASICs) are used for many of these scientific detectors. Until recently, pixel detector ASICs have been used mainly for analog signal processing of the charge from the sensor layer and the transmission of raw pixel data off the detector ASIC. However, with the availability of more advanced ASIC technology nodes for scientific application, more digital functionality from the computing domains (e.g., compression) can be integrated directly into the detector ASIC to increase data velocity. However, these computing functionalities often have high and variable latency, whereas scientific detectors must operate in real-time (i.e., stall-free) to support continuous streaming of sampled data. This paper presents an example from the domain of pixel detectors with on-chip data compression for X-ray science applications. To address the challenges of variablesized data from a parallel stream of compressors, we present an ASIC design architecture to coalesce variable-length data for transmission over a fixed bit-width network interface.

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A Hardware Co-design Workflow for Scientific Instruments at the Edge

Cited by 2 publications

References 29 publications

A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging

A lightweight, user-configurable detector ASIC digital architecture with on-chip data compression for MHz X-ray coherent diffraction imaging

Designing a Streaming Data Coalescing Architecture for Scientific Detector ASICs with Variable Data Velocity

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