A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping' is introduced. It is aimed at realistic fault assumptions prior to the Jinal layout by investigating typical "local layout structures of analogue designs. Specijk defects are assumed and their electrical failure modes are evaluated and mapped onto appropriate model faults. It is shown that some assumed hard faults at the schematic level are unrealistic and unlikely and that new types of fault constellations emerge including multiple or complex faults. Beside the different distribution of faults the overall number of faults decreases whereof additional realistic soft faults emerge. For an operational CMOS amplij2er the overall number of 47 single hard faults assumed at schematic level dropped to 27 realistic and likely hard faults. -Catastrophic Faults or Hard Faults -Deviation Faults or Soft Faults This research was performed within the ESPRIT I11 project ARCHIMEDES and supported by the European Union under grant 7107. Catastrophic faults, often also referred to as Hard Faults, are caused by random defects e.g. dust particles and can cause short and open circuits or large scale deviations of Paper 29.2 776 INTERNATIONAL TEST CONFERENCE 0-7803-3540-6196 $5.00 ' 1996 IEEE
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