A design for testability study on a high performance automatic gain control circuit

Abstract

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT)

Flexible embedded test solution for high-speed analogue front-end architectures

“…The results of testability analyses performed on representative analogue front-end components [28,31] and the interpretation of these for other high-speed architectures [32] provides evidence for superior test quality compared to conventional FFT-based testing. The kernel test time for the programmable gain block is reduced significantly while more time-consuming data capturing is avoided in A/D converter testing.…”

“…Further details and results are provided in [28]. To achieve good test quality, this part of the analogue front-end requires the assessment of gain step sizes and output voltage swing.…”

“…In this particular case, the flexible embedded test solution has been designed for an analogue front-end containing a 32-gain-set automatic gain control circuit and a 6-bit A/D converter. Details of the analogue front-end originally analysed in [28,31] and the designed test solution are listed in Table 1. Apart from the indication of window overflow discussed above, the designed circuitry also indicates overflow in DNL and INL computation and allows test application for both rising and falling ramp stimulus sections.…”

A digital partial built-in self-test structure for a high performance automatic gain control circuit

“…In this section a summary of the DfT study is provided, and further details can be found in [31]. The demonstrator is an AGC macro used to digitise sound signals.…”

“…As a result of the detailed study of the AGC design [31], the DfT guidelines above have been proposed. Based on this knowledge, a new AGC design has been studied, similar to that presented in Figure 1 but with resistor ladder layout structure according to the above DfT rule.…”