This paper presents a PWM strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15 kW motor drive prototype to validate the method effectiveness. Taking into account dead-time compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range.
In the simulation of power electronics systems, for reasons of computing time and convergence, it may be necessary to use ideal components which generate ideal voltage switchings (steep edges). However, in reality, these voltage variations are far from ideal and to reproduce a voltage closer to reality, it is necessary to model these variations. This is especially important for the study of residual voltage obtained by simultaneous switching, which are present in PWM strategies developped to reduce the impact of the common-mode voltage generated by 3-phase inverters. This paper is focused on the required model accuracy, in order to take into account these residues obtained by the synchronization of switching voltages.
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