PWM Strategy for the Cancellation of Common-Mode Voltage Generated by Three-Phase Back-to-Back Inverters

Abstract

This paper presents a PWM strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15 kW motor drive prototype to validate the method effectiveness. Taking into account dead-time compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range.

A New Filter Concept for High Pulse-Frequency 3-Phase AFE Motor Drives

“…However, both converters also generate a CM voltage that must be reduced for previously described reasons. In [9] it is demonstrated how the CM voltage waveforms in both converters can be made identical by sophisticated voltage pulse generation and thus the CM interference can theoretically be completely eliminated. In fact, in real experiments the CM voltage can be significantly reduced by more than 15 dB, although not completely, due to impediments such as different switching characteristics of the individual semiconductors or dead-time effects (cf.…”

“…In fact, in real experiments the CM voltage can be significantly reduced by more than 15 dB, although not completely, due to impediments such as different switching characteristics of the individual semiconductors or dead-time effects (cf. [9]). Another benefit of this measure is that a less saturation-resistant CM choke may be used, since the voltage-time areas, which need to be absorbed, are significantly smaller.…”

“…Furthermore, the reduction of the DC link voltage unburdens the inductive components, which have to absorb the main part of the voltage-time areas, with regard to the core and High Frequency (HF) copper losses. It can therefore be concluded that with the approach described in [9] flat-top modulation and the DC link voltage reduction would partially not be possible, leaving even more potential for optimization untapped. This is why it makes more sense to select the degree of freedom of the zero-voltage system for flat-top modulation.…”

Classification of Three-Phase Grid-Tied Microinverters in Photovoltaic Applications

“…There are two main concerns related to CMV, the common mode loop path and the source of CMV. Although many papers studied CMV reduction in non-isolated topologies of microinverters [20,47,48], CMV was not mitigated totally because the common mode is highly dependent on switching patterns, inverter operation, and design. On the other hand, High-Frequency Link (HFL) transformers integration can cut the common mode loop path.…”

Common-Mode and Phase-to-Ground Voltage Reduction in Back-to-Back Power Converters With Discontinuous PWM

“…However, with AZSVPWM, the harmonic distortion is greatly increased. v CM can even be eliminated by coordinating the modulations in GSC and MSC [9], but in this case the modulation in GSC is also modified affecting grid code compliance. All these modulations have the same number of commutations per switching period as the SVPWM7, and are based on the modification of the switching instants, so no improvement in efficiency is obtained.…”