IBM has made several quantum computers available to researchers around the world via cloud services. Two architectures with five qubits, one with 16, and one with 20 qubits are available to run experiments. The IBM architectures implement gates from the Clifford+T gate library. However, each architecture only implements a subset of the possible CNOT gates. In this paper, we show how Clifford+T circuits can efficiently be mapped into the two IBM quantum computers with 5 qubits. We further present an algorithm and a set of circuit identities that may be used to optimize the Clifford+T circuits in terms of gate count and number of levels. It is further shown that the optimized circuits can considerably reduce the gate count and number of levels and thus produce results with better fidelity.
Many modern programming languages rely on memory management environments that are responsible for allocation and deallocation of objects. Garbage collection phases are used in order to detect inaccessible objects on the heap so they can be deallocated. The performance of garbage collection techniques depends heavily on the environment, implementation specific parameters and the benchmark used. The contribution of this publication is an extendable memory management simulator, which aims to assist developers in memory management evaluation and research. The simulator is capable of reading operations from a trace file extracted from a virtual machine and simulating the memory management needed by the simulated mutator. The framework aims to provide an isolated experimentation and comparison platform in the field of automatic memory management. New algorithms can be added to the framework in order to compare them to established algorithms.
The Toffoli gate, as originally proposed, had only positive controls. It has been shown that mixed polarity controlled Toffoli gates can be efficiently implemented. In fact, their quantum cost is the same as for positive controlled gates in most cases. Thus it is advantageous to consider circuits with mixed polarity Toffoli gates. Template matching has been successfully used to reduce the number of Toffoli gates in reversible circuits. Little work on templates with mixed polarity gates has been reported. Unfortunately, the number of potential templates increases dramatically, if mixed polarity is introduced. Here we propose a dynamic template matching algorithm that takes templates with few lines and dynamically extends the lines to find matches. Experimental results show that the proposed approach has a significant impact on reducing the total number of gates (57% in the best case) in circuits.
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