A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a lowrank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.
In this article, a Field Programmable Gate Array (FPGA)‐based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right‐hand‐side (RHS) vectors, the computational cost for multiple matrix‐vector products presents a time bottleneck in a linear‐complexity fast solver framework. In this work, an FPGA‐based hardware implementation is proposed toward a two‐level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple‐RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed‐ups over 10× against equivalent software implementation on a 2.4 GHz Intel Core i5 processor is achieved using a Virtex‐6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200 MHz clock frequency. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776–783, 2016
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