Initial timing acquisition in narrow-band IoT (NB-IoT) devices is done by detecting a periodically transmitted known sequence. The detection has to be done at lowest possible latency, because the RF-transceiver, which dominates downlink power consumption of an NB-IoT modem, has to be turned on throughout this time. Auto-correlation detectors show low computational complexity from a signal processing point of view at the price of a higher detection latency. In contrast a maximum likelihood cross-correlation detector achieves low latency at a higher complexity as shown in this paper. We present a hardware implementation of the maximum likelihood crosscorrelation detection. The detector achieves an average detection latency which is a factor of two below that of an auto-correlation method and is able to reduce the required energy per timing acquisition by up to 34%.
EDGE-based EC-GSM-IoT is a promising candidate for the billion-device cellular IoT (cIoT), providing similar coverage and battery life as NB-IoT. The goal of 20 dB coverage extension compared to EDGE poses significant challenges for the initial network synchronization, which has to be performed well below the thermal noise floor, down to an SNR of −8.5 dB. We present a low-complexity synchronization algorithm supporting up to 50 kHz initial frequency offset, thus enabling the use of a low-cost ±25 ppm oscillator. The proposed algorithm does not only fulfill the 3GPP requirements, but surpasses them by 3 dB, enabling communication with an SNR of −11.5 dB or a maximum coupling loss of up to 170.5 dB.
Brain-inspired high-dimensional (HD) computing represents and manipulates data using very long, random vectors with dimensionality in the thousands. This representation provides great robustness for various classification tasks where classifiers operate at low signal-to-noise ratio (SNR) conditions. Similarly, hyperdimensional modulation (HDM) leverages the robustness of complex-valued HD representations to reliably transmit information over a wireless channel, achieving a similar SNR gain compared to state-of-the-art codes. Here, we first propose methods to improve HDM in two ways: (1) reducing the complexity of encoding and decoding operations by generating, manipulating, and transmitting bipolar or integer vectors instead of complex vectors; (2) increasing the SNR gain by 0.2 dB using a new soft-feedback decoder; it can also increase the additive superposition capacity of HD vectors up to 1.7$$\times$$ × in noise-free cases. Secondly, we propose to combine encoding/decoding aspects of communication with classification into a single framework by relying on multifaceted HD representations. This leads to a near-channel classification (NCC) approach that avoids transformations between different representations and the overhead of multiple layers of encoding/decoding, hence reducing latency and complexity of a wireless smart distributed system while providing robustness against noise and interference from other nodes. We provide a use-case for wearable hand gesture recognition with 5 classes from 64 EMG sensors, where the encoded vectors are transmitted to a remote node for either performing NCC, or reconstruction of the encoded data. In NCC mode, the original classification accuracy of 94% is maintained, even in the channel at SNR of 0 dB, by transmitting 10,000-bit vectors. We remove the redundancy by reducing the vector dimensionality to 2048-bit that still exhibits a graceful degradation: less than 6% accuracy loss is occurred in the channel at − 5 dB, and with the interference from 6 nodes that simultaneously transmit their encoded vectors. In the reconstruction mode, it improves the mean-squared error by up to 20 dB, compared to standard decoding, when transmitting 2048-dimensional vectors.
System specification of SoCs needs to be supported by quantitative cost models to avoid wrong decisions in this early design phase. For less complex logic structures like for example FIR filters such generic cost models can be derived easily because they base on a simple gate count. For LDPC decoders the influence of the global interconnect between the two basic components of such a decoder complicates the derivation of general cost models. This might be the reason why no accurate cost models are known from literature yet. In this paper generic silicon area, iteration period, and energy cost models of high-throughput LDPC decoders are derived. Those models do not only allow for a decoding-performance vs. hardware-cost trade-off analysis during system specification but can also be used later on to choose a suitable architecture for a certain specification. Finally these models can be used for a fair benchmarking of the implemented decoder. I.INTRODUCTION LDPC decoders show an outstanding error correction performance which almost reaches the Shannon limit. Therefore they are applied in most of next generation communication standards. Typically the throughput and possibly the latency of the decoder are specified. Additionally there is a third requirement which is the guarantee of a certain bit error rate (BER). If those hard requirements are met other decoder features such as silicon area and energy per bit can be optimized.A decoder loop of a bit-parallel Min-Sum algorithm based LDPC decoder [1] is illustrated in Fig. 1. In the block diagram only one of the n bit and one of the m check nodes are depicted. Each check node consists of a minimum search which compares the magnitudes of the a-priori information L(q) received from the d C connected bit nodes and finds the two minima. To each connected bit node either the first or second minimum is sent as a-posteriori information L(r). In the bit node the information of the d V connected check nodes and the received noisy channel symbols are accumulated leading to a corrected estimation of the received symbol.In regular codes all bit (check) nodes are connected to d V (d C ) check (bit) nodes. Therefore the interconnect consists of 2·n·d V ·w interconnect lines with w being the word length of one message. Due to this complex interconnect the utilization of the active silicon area is very low (e.g. 50 % in [2]). As discussed in [3] the choice of a bit-serial decoder to reduce the interconnect complexity leads to a relatively low decoder throughput as two data flow swaps are required in one
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