Chemical mechanical polishing (CMP) is rapidly becoming the process of choice for planarizing dielectrics in very large scale integrated circuits. In addition, it is being used at an increasing rate in the removal of metals in order to define conducting levels. In the case of dielectric CMP, planarization ability is dictated by the mechanical aspects of polishing such as pad rigidity, polishing pressure and speed of the polishing platen, while inherent removal rate of the dielectric material is generally a function of the polishing chemistry. Polishing rate of both, dielectric and metallic films can be significantly increased by changing the nature of the dispersed abrasive in the slurry and that of the dispersing agent. However, such changes have profound implications to the surface quality, planarity, and cleaning of the polished surface. In addition, the polishing pad plays an important role in manufacturability of metal CMP processes. This work reviews the chemistry of polishing slurries containing silica, ceria and alumina abrasives for dielectric and metal CMP. Also, the contribution of the polishing pad to CMP processes is explained. The need for balancing the chemical and mechanical aspects of polishing in order to achieve overall planarization and pattern definition is demonstrated.
As recently as 1993, the prevailing presumption among the semiconductor technical community was that then-current development efforts associated with aluminum lines and tungsten damascene vias needed to shift rapidly to copper multilevel interconnect schemes. This is exemplified by the June 1993 issue of the MRS Bulletin, which featured copper metallization as its theme. In the intervening years, however, that same technical community revised the Semiconductor Industry Association (SIA) roadmap and placed renewed emphasis on the use of an all-aluminum interconnect scheme. This was done largely in deference to the costs associated with converting existing semiconductor lines to copper-compatible facilities. In addition to tooling costs, there is a learning curve for copper systems that remains to be established for device reliability, field failures, yield learning, and process maturation. On the other hand, existing fabs are already compatible with aluminum metallurgies, and there is a rich history of reliability and yield data.This change in direction creates two immediate needs: (1) the need to fill small-diameter vertical interconnects (vias) with void-free aluminum and (2) the need to remove the top surface aluminum resulting from its blanket deposition (overburden) following the metal fill. In addition, for high circuit-density applications, it may be desirable, if not necessary, to form the metal lines using the same damascene fill method as is used for the vias. This process strategy replaces metal etching and insulator gap fill with insulator (usually silicon oxide) etching and metal gap fill.
Methods for determining planarization ability of CMP were explored. Options included film thickness measurements of the dielectric over metal and field, TIR measurements using profilometry, and a combination of the two. The attempt to observe the in situ change in the topography was addressed in two distinct experimental approaches. The first approach involved processing wafers for predetermined intervals. The other approach processed different wafers for different amounts of time. The effects of down force and platen rpm on planarization ability were studied using the first approach. Results indicate that planarization is more efficient at higher down forces and higher platen rpm. Slurry property effects were examined using the second method. The planarization ability appears to suffer at elevated pH values. This is attributed to both the enhanced solubility of the silica particles and the dielectric itself.
Global Planarization requirements of the deep sub-micron technology generation requires use of CMP as preferred planarization technique. In the past, CMP has been used extensively in the polishing of silicon wafers. However , there has been some reluctance to utilize this technology in the planarization of oxide films during IC manufacture. This has been driven primarily by issues regarding manufacturability , and therefore cost of ownership of CMP processes. Here the key process integration issues in CMP planarization of oxide films are outlined.An effect of consumable set is shown to be critical in achieving repeatable CMP performance via removal rate & non-uniformity. Various defects induced as a result of CMP are explained. Cost of ownership model is used to demonstrate the importance of minimizing such defects.
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