Logic emulation enables designers to functionally verify complex integrated circuits prior to chip fabrication. However, traditional FPGA-based logic emulators have poor interchip communication bandwidth, commonly limiting gate utilization to less than 20%. Global routing contention mandates the use of expensive crossbar and PC-board technology in a system of otherwise low-cost commodity parts. Even with crossbar technology, current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires, and pipelining these connections at the maximum clocking frequency of the FPGA. The resulting increase in bandwidth allows effective use of lowdimension direct interconnect. The size of the FPGA array can be decreased as well, resulting in low-cost logic emulation. This paper covers major contributions of the MIT Virtual Wires project. In the context of a complete emulation system, we analyze phase-based static scheduling and routing algorithms, present virtual wires synthesis methodologies, and overview an operational prototype with 20K-gate boards. Results, including in-circuit emulation of a SPARC microprocessor, indicate that virtual wires eliminate the need for expensive crossbar technology while increasing FPGA utilization beyond 45%. Theoretical analysis predicts that virtual wires emulation scales with FPGA size and average routing distance, while traditional emulation does not.
We describe a complete FPGA-based emulation software system using Virtual Wires technology and present the results of emulating an 18K-gate ASIC implementation of a modified Sparc microprocessor. Virtual Wires overcomes the pincount limitation that formerly restricted the efficiency of FPGA-based logic emulators. The MIT Virtual Wires softwire compiler accepts a netlist description of the system to be emulated and produces programming information for the FPGA hardware, an inexpensive ($3000) board designed for Virtual Wires in-circuit emulation. The compiler also provides an interface to standard logic simulator tools for hardware accelerated simulation. We discuss innovative features of the compiler system and knowledge gained during its construction. A comparison is made of different implementations of the on-chip Virtual Wires circuitry synthesized by the compiler. Several enhancements to the original Virtual Wires concept are presented that will further emulation speed and FPGA utilization.
With the popularity and development of the internet and mobile terminals, people can access a lot of information through them every day. Recommender systems have become one of the important technologies for various online platforms that aim to predict whether a user will interact with an item or not. Among them, collaborative filtering-based models have made effective progress in learning user and item representations by modeling historical user-item interactions. Recently, models based on GCN have been effective in recommendation, and the main function of GCN models is to improve the embedding representation of users and items by iteratively aggregating feature information from neighbors using graph connectivity to extract additional information. However, in previous works, dividing users into subgraphs without intersection only leads to a partial loss of information, ignoring the potential connections that may exist between different groups of users; and because only users are divided, the influence of commodity factors on the purchase outcome at the time of purchase is ignored in the learning process. Based on the above considerations, in this paper we propose a message-passing recommendation model. The model uses intersects users and items in separate subgraphs and uses an optimized attention mechanism to obtain the final node embedding to optimize the embedding representation by introducing multiple embedding propagation layers that encode higher-order connectivity relationships. We conduct extensive experiments to evaluate the proposed model. The results show that our model can effectively improve the performance of the recommendation.
TIERS is a new pipelined routing and scheduling algorithm implemented in a completeVirtualWire TM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.
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