Logic emulation with virtual wires

Babb, Jonathan; Tessier, Russell; Dahl, Matt; Hanono, Silvina Zimi; Hoki, David M.; Agarwal, Anant

doi:10.1109/43.640619

Cited by 126 publications

(46 citation statements)

References 19 publications

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“…Previous work suggests that such a situation can be avoided by limiting the size of asynchronous-domain logic to one FPGA or by dedicating special inter-FPGA wires to transport the values (hard-wiring) [4]. Since hard-wired signals cannot be multiplexed to carry non-MTSD nets, pin limitation problems [2] can result, leading to reduced system performance. To avoid this problem, it is desirable to split a multidomain value into constituent domain values, route (schedule) the values in respective domains, and recover the multidomain value at the destination FPGA.…”

Section: If Part a Feeds Part B Events On A Must Have Occurred Beformentioning

confidence: 99%

“…To avoid this problem, it is desirable to split a multidomain value into constituent domain values, route (schedule) the values in respective domains, and recover the multidomain value at the destination FPGA. This solution poses another problem because of unpredictable route timing that is inherent in statically routed systems [2].…”

Section: If Part a Feeds Part B Events On A Must Have Occurred Beformentioning

confidence: 99%

“…Since many combinational evaluations and signal transfers may occur in a single design clock cycle, the Virtual Clock by necessity runs at a much higher frequency than the design clock. Additional detailed discussion of virtual wires compilation can be found in [2] and [16]. A preliminary approach for scheduling latch evaluation for asynchronous clock domains in logic emulation systems is described in [10].…”

Section: The Target Systemmentioning

confidence: 99%

“…As a final step, compilation for each logic processor is performed. This step includes FPGA place and route for FPGA-based logic emulators [2] and Boolean instruction scheduling for special-purpose logic processors [13].…”

Section: B Verification Software Flowmentioning

confidence: 99%

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Static scheduling of multidomain circuits for fast functional verification

Kudlugi

Tessier

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This design characteristic presents a significant challenge when these ASIC designs are mapped to parallel verification hardware such as parallel cycle-based simulators and logic emulators. In general, these systems require all computation and communication to be synchronized to a global system clock. As a result, the undefined relationship between design clocks can make it difficult to determine hold times for synchronous storage elements and causality relationships along reconvergent communication paths. This paper presents new scheduling and synchronization techniques to support accurate mapping of designs with multiple asynchronous clocks to parallel verification hardware. Through analysis, it is shown that this approach is scalable to an unlimited number of domains and supports increasingly large design sizes. To prove the effectiveness of the authors' approach, developed algorithms have been integrated into the compilation system for a commercial multi-FPGA logic emulation system. For three designs mapped to a logic emulator using this software environment, modeling fidelity is maintained and performance is enhanced versus previous manual mapping approaches. A theoretical analysis based on Rent's rule validates the scalability of the approach as device sizes increase.

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Section: If Part a Feeds Part B Events On A Must Have Occurred Beformentioning

confidence: 99%

Section: If Part a Feeds Part B Events On A Must Have Occurred Beformentioning

confidence: 99%

Section: The Target Systemmentioning

confidence: 99%

Section: B Verification Software Flowmentioning

confidence: 99%

See 2 more Smart Citations

Static scheduling of multidomain circuits for fast functional verification

Kudlugi

Tessier

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

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“…sequential code, loop-level parallelism, and subroutine functions. Based on calling patterns, dataflow dependency between blocks is determined through both forward and reverse tracing of interblock paths [17]. As a result of this dependence analysis, coarse-gained blocks can be scheduled to promote parallel computation.…”

Section: B Basic Block Partitioning and Assignmentmentioning

confidence: 99%

An architecture and compiler for scalable on-chip communication

Liang

Laffely²,

Srinivasan

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-m technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four.Index Terms-Communications architecture, on-chip interconnect, system-on-chip (SoC).

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Reconfigurable Computing

Chung-Kuan¹,

Kahng²,

Leong³

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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This paper describes our approach to adapting a text document similarity classifier based on the Term Frequency Inverse Document Frequency (TFIDF) metric to two massively multi-core hardware platforms. The TFIDF classifier is used to detect web attacks in HTTP data. In our parallel hardware approaches, we design streaming, real time classifiers by simplifying the sequential algorithm and manipulating the classifier's model to allow decision information to be represented compactly. Parallel implementations on the Tilera 64-core System on Chip and the Xilinx Virtex 5-LX FPGA are presented. For the Tilera, we employ a reduced state machine to recognize dictionary terms without requiring explicit tokenization, and achieve throughput of 37 MB/s at a slightly reduced accuracy. For the FPGA, we have developed a set of software tools to help automate the process of converting training data to synthesizable hardware and to provide a means of trading off between accuracy and resource utilization. The Xilinx Virtex 5-LX implementation requires 0.2% of the memory used by the original algorithm. At 166 MB/s (80X the software) the hardware implementation is able to achieve Gigabit network throughput at the same accuracy as the original algorithm.

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Logic emulation with virtual wires

Cited by 126 publications

References 19 publications

Static scheduling of multidomain circuits for fast functional verification

Static scheduling of multidomain circuits for fast functional verification

An architecture and compiler for scalable on-chip communication

Reconfigurable Computing

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