In this paper we present a customized approach to performance and area optimization of asynchronous functional blocks. First an abstract model of the block architectwe is introduced and an analytical method for throughput maximization is described. Secondly, area optimization can be performed with respect to data dependencies and merged data paths. These methods have been implemented and validated by several examples. A first chip implementing all relevant architecture blocks has been produced. The chip is named FLYSIG~ and operates completely delay-insensitive.
The implementation of real-time communication within the design of embedded systems becomes more and more the real system bottleneck. For this reason the evaluation of the communication characteristics is very essential in an early design stage. In this paper we present an evaluation method for real-time communication based on rapid prototyping. Key points are the ISO/OSI layer conform implementation, exchangeable hardware and software modules and the adaptation of a wide range of real-time protocols. These aspects are implemented and illustrated in our casestudy: Two interacting robots with five degrees of freedom, each.
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