This paper presents a new design template and design flow for the implementation of data-driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only storage elements, not only for the datapaths, but also for the control circuits; latches and C-elements that are common in many asynchronous circuit design styles are not required. The design template uses a two-phase handshake protocol for inter-component communication. In a pipeline structure, these circuits operate near the speed of Mousetrap circuits, but the required design-flow is simpler. The implementation stylewhich we refer to as Click elements -has been chosen to resemble synchronous circuits as much as possible. This allows for the use of conventional optimization and timing tools in the design flow and for a cheaper design-for-test implementation. The click templates are well suited for a data-flow driven compilation flow, which avoids much of the control overhead of traditional syntax-directed compilation. The two-phase circuits show a significant improvement in performance and energy efficiency compared to four-phase single-rail circuits.
IntroductionDynamic reconfiguration of FPGAs has recently become viable with the introduction of devices that allow high speed partial reconfiguration, e.g., the Xilinx XC6200 series [14]. Dynamic reconfiguration is usually performed by a software system that decides when to reprogram part of the FPGA and with what. The simplest kind of run-time software simply selects a precompiled circuit and transmits the programming data directly to the FPGA. At the University of Glasgow's Department of Computing Science, the Reconfigurable Architecture Group (RAGE) has a number of projects examining applications of dynamic reconfiguration. These applications have highlighted the need for a more complex run-time system. Rather than developing different run-time systems for each application, as is common, we have extracted a set of common requirements from several applications. This has formed the basis of the design of a proposed, core, run-time system, able to support all of these applications. There are many parallels that can be drawn between this design and conventional operating system design-as the techniques used to manage conventional resources, such as memory and the CPU, are also applicable to the management of FPGAs.The next section of this paper describes three applications of dynamic reconfiguration and their requirements, and draws from these a set of core requirements. We follow this with an overview of the proposed system, and more detailed discussions of the rôles of the identified system components. We close with a discussion of how our system might support other applications in the field.
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