This paper presents a Model Driven Engineering approach for MPSoC Design Space Exploration (DSE) to deal with the evergrowing challenge of designing complex embedded systems. This approach allows the designer to automatically select the most adequate modeling solution for application, platform, and mapping between application and platform, in an integrated and simultaneous way and at a very early design stage, before system synthesis and code generation have been performed. The exploration is based on high-level estimates of physical characteristics of each candidate solution. In an experimental setting, the DSE tool automatically performs four design activities: it selects the number of processors, maps tasks to processors, allocates processors to bus segments, and sets the voltage of each processor. Experimental results, extracted from a DSE scenario for a real application, show that the proposed estimation and exploration approach may find a suitable solution regarding the design requirements and constraints in a very short time, with an acceptable accuracy, without relying on costly synthesis-and-simulation cycles.
The IEEE-1800 SystemVerilog [20] system description and verification language integrates dedicated verification features, like constraint random stimulus generation and functional coverage, which are the building blocks of the Universal Verification Methodology (UVM) [3], the emerging standard for electronic systems verification. In this article, we introduce our System Verification Methodology (SVM) as a SystemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus generation. Thereafter, we introduce the SVM with advanced TLM support based on SystemC and compare it to UVM and related approaches. Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle.
In this paper we propose an embedded software design flow, which starts from an UML model and provides automatic mapping to other models like Simulink or finite-state machines (FSM). An automatic synthesis of an executable and synthesizable Simulink model is also proposed, enabling the use of UML as front-end for a multi-model design strategy that includes a Simulinkbased MPSoC target design flow. In addition, the proposed synthesis tool automatically handles processor allocation, mapping of threads to processors, and insertion of required Simulink temporal barriers, ports, and dataflow connections. Following this approach, the UML model is mapped to the more appropriated model and specialized code generators are used. Therefore, this approach allows designers to employ UML to model the whole system and reuse this model to generate code using different strategies and targeting different platforms.
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