This paper presents a butterfly physically unclonable function (PUF) implementation in SRAM-based field programmable gate arrays (FPGAs). To avoid output instability, we propose a delay difference test to identify reliable slices (mapped to which butterfly PUF cells are highly reliable) and then PUF reliability is significantly improved by selective mapping PUF cells to reliable slices, which is validated in experimental results.
Security is critical to the growing popularity of the Internet of Things(IoT), and true random number generator (TRNG) plays an increasingly important role in information security systems. Conventional TRNGs use natural physical stochastic processes including thermal noise, chaos-based circuit, and so on to generate random numbers. These analog circuits based TRNG structures often consume excessive hardware resources. Meanwhile, it is difficult to incorporate them into digital system. In this paper, a novel all-digital true random number generator in SRAM-based FPGAs is proposed by using Vernier technique that precisely quantize random edge jitter. The proposed TRNG design is implemented on Xilinx Virtex-6 XC6VLX240T-1FF1156 FPGA and shows a high quality of randomness which has passed the NIST test suite with relatively high p-values, achieves a high throughput of 127 Mbps with occupying 32 slices. Experimental results show a good tolerance to bias phenomenon induced by process, voltage, and temperature variations. INDEX TERMS true random number generator, Vernier technique , field programmable gate array, high throughput
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