In this paper, the fabrication and material innovation involved in the first and only entirely inkjet-printed polysilicon thin film transistors (TFTs) are described. To form TFT layers, five inkjet printing inks were developed with the goal of fabricating TFTs by using purely additive processing without vacuum deposition or conventional lithography. A silicon ink was developed to form both the channels and polysilicon gates, and boron and phosphorus dopant inks were developed for N+ and P+ doping. In addition, a silver nanoparticle (NP) ink was developed to form interconnect traces, and a palladium chloride ink was formulated to create palladium silicide for the ohmic contacts between the source and the drain. The first N-type metal-oxide-semiconductor (MOS) polysilicon TFT was fabricated with a top-gate self-alignment scheme. This exhibited a mobility of approximately 80 cm2 V s−1. Next, P-type MOS transistors as well as complementary MOS devices were also successfully fabricated.
To move the promise of printed electronics from the laboratory to volume production required adopting a new approach eliminating ink-jet printing and adopting instead a hybrid mature print and conventional process. Novel screen printable N+ and P+ dopant inks were developed to fabricate polysilicon thin film transistors (TFTs). Semiconductor-grade dopant inks were formulated from a combination of thermoset plastic with boron and phosphor compounds. Inks were screen printed on polysilicon active islands on a 300 mm square stainless-steel foil substrate. The drain and source of the top gate TFTs were then formed via a thermal anneal activation. The residue after annealing was removed with an inoffensive process to avoid damage to the thin silicon layer and gate oxide. Doping was uniform across 300 mm sheet substrate. The sheet resistance was modulated to 200 Ω sq−1 for the N+ and 1000 Ω sq−1 for the P+ active layer. Field mobility of polysilicon TFTs fabricated using this screen-printed dopant process were 80 cm2V s−1 for PMOS and 200 cm2V s−1 for NMOS using low-cost, mature equipment, and an easily manageable process that is both scalable and compatible with roll-to-roll manufacturing.
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