Abstract-The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded Software Metadata information is especially important today, because several complex multi-threaded applications are mapped on the memory of a single embedded system. Each thread is triggered at run-time by different input events that can not be predicted at design-time. New methods and tools are needed to automatically profile and analyze the dynamic data access behavior of simultaneously executing threads in order to enable memory data transfer optimizations. In this paper, we propose such a method and tool which extract the necessary Software Metadata information to enable these data transfer optimizations at the system level. We assess the effectiveness of our approach with the results for five real-life software applications using seven real-life run-time input traces.
The design exploration procedure of DSP systems using simulation tools is a time-consuming process, even for low complexity applications. The main goal of the design methodology introduced in this paper is to provide fast and accurate estimates of the number of (-micro) instructions and the instruction cache miss rate of DSP applications implemented on a programmable embedded platform, during the early design phases. Specific information is extracted from both the high-level code description (C code) of the DSP application considered and its corresponding assembly code, without carrying out any kind of simulation. The proposed methodology requires only a single execution of the application in a general-purpose processor and uses only the assembly code of the targeted embedded processor. In order to automate the estimation procedure, a new software tool, which implements the proposed methodology, has been developed. Using nine real-life applications from different domains of the DSP field, it has been proved that with the proposed methodology the number of instructions and the miss rate of instruction cache can be estimated with high accuracy (>95%). Furthermore, the required time cost is much smaller (orders of magnitude) than the simulation-based approaches.
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