Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information

Abstract

Abstract-The information about the run-time behavior of software applications is crucial for enabling system level optimizations for embedded systems. This embedded Software Metadata information is especially important today, because several complex multi-threaded applications are mapped on the memory of a single embedded system. Each thread is triggered at run-time by different input events that can not be predicted at design-time. New methods and tools are needed to automatically profile and analyze the dynamic data access behavior of simultaneously executing threads in order to enable memory data transfer optimizations. In this paper, we propose such a method and tool which extract the necessary Software Metadata information to enable these data transfer optimizations at the system level. We assess the effectiveness of our approach with the results for five real-life software applications using seven real-life run-time input traces.

Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform

“…In contrast to previous work, [5] instruments just the dynamic memory management primitives along with all the accesses to memory. A data identification algorithm is proposed and based on the results, DMA optimizations are implemented.…”

Dynamic Memory Management for Embedded Systems

“…Therefore, the information regarding the behavior of the application in terms of its dynamic memory consumption must be collected at run-time. As such, the method starts with a metadata collection step before the different optimization steps are applied, resulting in a method flow to tackle dynamic memory [22].…”

“…The second one uses the DMA module for blocks of more than 32 bytes (eight words), but the maximum number of cycles that the DMA engine may hold the bus during burst transactions is limited to eight words (therefore, once the DMA is granted access to the bus, it can transfer without interruptions at least as many bytes as the shortest transfer). Finally, the third configuration employs the DMA module for transfers of at least 32 bytes, but ensures that the DMA may access up to a full DRAM page in a single burst transaction to maximize the efficiency; additionally, this last policy uses the techniques presented in [135] and [22] to decide whether to use the DMA module or not if the system can recognize the current input case. We refer to these policies as "No DMA," "DMA Bad" and "DMA Opt", respectively.…”

“…This ensures that no comparisons between individual DDTs, but between the DDTs and the groups, are done, reducing the algorithm complexity. To evaluate the inclusion of a DDT in a group, the new combined behavior is calculated (lines [22][23]. This is a straightforward process that involves combining two ordered lists and accounting for the accumulated footprint and accesses of the group and the DDT.…”

Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs

“…More information about this application and the network traces can be found in [34]. The case study was evaluated on a cycle-accurate Network-on-Chip (NoC) simulation environment [18].…”